Nano, when a wavelength is huge

Database units: how layout files store coordinates as integers A GDSII or OASIS file stores every coordinate as a whole number of database units. How that scale becomes microns, and what breaks when tools disagree. Drawing circles in a layout: polygons, side count, and arc error A layout file saves a circle as a many-sided polygon. How many sides to use, how far the flats sit inside the true radius, and what the mask shop will see. Overlapping is not merging Two shapes sharing coordinates are still two objects. A merge is one outline. Factories care which you meant. Channels, not wires A path that liquid occupies. Width is hydraulic. Dead volumes are the new parasitics. Text on a layout: labels, printed letters, and what the mask shop ignores A GDS text record is a string on a layer; convert it to polygons before a mask shop must print it. SKY130 68/5 labels stay unchecked; 68/20 outlines are measured. Merging polygons A merge replaces overlapping shapes on one layer with a single outline of the area they cover. Here is how that outline is computed, what the file stores, and where it goes wrong. Vias and contacts in IC layout: cut layers, enclosure, and via rows Vias and contacts in a chip layout: the cut layers between floors, SKY130 via size, spacing and enclosure rules, via rows, and what a DRC cannot see. Polygons in a layout: vertices, holes, and why a box is not enough A layout polygon is a closed list of vertices on one layer: how GDSII and OASIS store it, vertex order and area, holes as cut lines, broken polygons, vertex limits, and how to check them in LayoutEditor. Holes in polygons A window in metal is a void in a polygon — keyhole, boolean NOT, or a stacked-solid lie. Merge can fill what you meant to keep open. Design rules and DRC: real rule values and how to read a marker Design rules are the factory's limits in numbers; DRC is the spellchecker that measures them. SKY130 width, space, and enclosure values, rule flags, how to write and test a .ledrc rule deck by hand, and why deleting a marker fixes nothing. A PCB stackup The sandwich recipe: foils, cores, which copper is which file. Layout names must match this, not your mood. Alignment marks and registration Alignment marks are paired shapes on two mask levels that let an aligner, stepper, or writer place each new level on the pattern already on the wafer. Analog layout is furniture: matching, dummies, and guard rings Identical schematic devices come out different on silicon. Pelgrom's area law, stress and well-edge effects, common centroid, dummy fingers, and guard-ring rules from an open PDK. Antenna rules: charge during etch Antenna rules limit the conductor area connected to a transistor gate during manufacturing, because plasma etching charges the wire; jumpers and antenna diodes fix violations. Cell arrays and step-and-repeat: rows, columns, pitch, and AREF An array places one cell in rows and columns at a fixed pitch and is stored as one array reference (AREF in GDSII). How a wrong step adds up across the grid, and why one record has one rotation. AND, OR, NOT, XOR: layout as sets A boolean asks where two layers overlap, combine, or differ, and answers with new polygons. Transistor gates, clearances, masks, and layout comparisons are all computed this way. Boxes are just rectangles An axis-aligned rectangle is a native four-number object. Rotate, chamfer, or boolean it and it becomes a polygon. Cells and instances Draw the pad once and stamp it many times. Each stamp is the same drawing in a new place, not a photocopy of the ink. Density rules and fill: why empty space gets dummy shapes A density rule limits how much of each window a layer may cover. Real window sizes, why polishing cares, how fill repairs a sparse region without touching the circuit, and how to fill and check a layout in LayoutEditor. The drawing is not the thing you build Glass, silicon, and fiberglass are different objects that can share one geometry. DXF from the mechanical world Arcs, inches, and layers with names like ‘Contour’. Translation is culture as much as geometry. E-beam direct write vs. mask writing: Gaussian, VSB, and multi-beam E-beam lithography writes a layout into resist without a mask, either on the wafer (direct write) or on a photomask blank; Gaussian, VSB, and multi-beam writers differ in shot count, write time, and resolution. Enclosure is a frame for misalignment The inner feature has to sit on an island big enough that the factory’s slop cannot knock it off. Extruding into the third dimension Give each layer a thickness and the top view becomes a toy building. Honest only if the thicknesses are. Hierarchy and flattening: why chips keep cells and boards go flat Flattening replaces cell references with transformed copies of their shapes: what GDSII SREF and AREF records store, how the transform is applied, what it costs in file size, and how to flatten and check a layout in LayoutEditor. Footprints are almost cells A footprint is drawn once and placed many times, so its pads, paste, courtyard, and pin 1 must be right in that one master. From idea to something a shop can print How a napkin sketch becomes a file, a cover letter, and a glass plate a shop can print from. Layer and datatype: the two-number name 31/0 is not a street address. It is how GDS remembers two meanings on one film. GDSII in plain language A 1970s suitcase that still carries almost every chip drawing on Earth. What is a Gerber file? The plot format for PCB layers A Gerber file is a text file that describes one layer of a printed circuit board as a 2D vector image built from apertures, flashes, draws, and regions. How a MOSFET is drawn A transistor on a chip drawing is a top-view sandwich of active, poly, well, implant, and contact — not the schematic symbol. Keepouts and blockages A keepout or blockage is a drawn region that is never manufactured; it tells a router, placer, fill generator, or board checker which objects may not be placed inside it. One of two adjacent sides: checking m1.5, li.5, and via.5a in .ledrc Some contact rules let the metal be thin on one side, or on two opposite sides, but never on two sides that meet at a corner. How to read that rule in the SKY130 table, write it by hand as one LayoutEditor check line, and prove it on a layout built to fail. LEF and DEF in plain language LEF describes the layers, vias, sites, and cell abstracts of a digital library; DEF describes one design built from it, with die area, rows, placed instances, pins, power grid, and wires. Looking at a cross-section A side view of the sandwich. Layout is the top of this. MEMS people live here. LVS: layout versus schematic, and how to read the report Schematic and layout describe one circuit in two languages. How LVS extracts nets from polygons, a LayoutEditor script that checks a layout against a SPICE netlist and against a schematic, and how to read opens, shorts, and device mismatches. Manhattan versus all-angle Manhattan layouts use only horizontal and vertical edges; 45-degree and all-angle layouts allow slants and curves. The choice changes wire length, how gaps are measured, which corners land on the grid, which rules apply, and what the mask costs. MEMS is layout plus a recipe The top view is not enough. You need the sandwich: deposit, etch, release. Nets, pins, and labels on a layout Geometry alone is not a netlist: labels name joined metal, pins mark where a named net may enter a cell. OASIS vs GDSII: when GDS gets huge OASIS (SEMI P39) can store a repeated shape as one record plus a repetition, so contact, via, and fill fields take less space than in GDSII; unique polygons do not get smaller. Optical proximity correction (OPC) Optical proximity correction changes the mask after layout, with serifs, hammerheads, biases, and assist bars, so that the printed pattern matches the drawn shapes. Layout origin and quadrants: where (0,0) sits and which way Y grows Every cell has an origin and a Y direction. Disagree on zero or up, and every instance lands in the wrong place. Paths in layout: centerline, width, end caps, and bends A layout path stores a centerline and one width. How end caps and corners are built, when a path turns into a polygon, and how a wrong cap causes an open or a short. PCB copper is a layer too Board copper foil is still a named layer — traces, pads, and pours on a sheet, not chip metal film. PCells: cells with knobs A parameterized cell is a layout recipe: set width, counts, or pitch, and a script builds or reuses a uniquely named cell. LayoutEditor macros, naming, and what you freeze before the fab. Process layers versus drawing layers Some sheets become matter. Some sheets are notes to tools and humans. Do not chrome the notes. Reading a layer map How to turn a factory's table of number pairs into names, purposes, and masks — so you know which shapes become metal and which are only notes. Snapping, and the quiet disaster of off-grid points The magnet on your cursor is how drawings stay manufacturable. Turn it off and you will invent illegal corners. Steppers and why size matters The machine prints a field, then steps. Your die has to fit that window, not only the wafer. Select, move, stretch, copy: editing layout without breaking it How the selection in LayoutEditor decides between move and stretch, why a pad moved alone opens a joint without a DRC error, which SKY130 rules a stretch can break, and how copies differ from cell references, with tested LayoutScript and .ledrc examples. Layout grids: display grid, database unit, and manufacturing grid A corner can sit on the display grid and still miss the manufacturing grid. How the three grids differ, and why an off-grid corner is rounded by the mask writer and can fail a space check. Waveguide layout: bend radius, width, and paths on a photonic chip A waveguide is a path that light follows. Width sets the mode, a tight bend radiates, and the bend radius is part of the device, not a routing convenience. What a DRC rule deck is A DRC rule deck is the file that turns a rule manual into layer definitions, derived layers, checks, and named report categories that a design-rule-check tool runs on a layout. What a layer is for: layer numbers, purposes, and hiding sheets A layer is a sheet the factory spends a process step on. GDS layer/datatype pairs with real SKY130 numbers, drawn vs derived layers, and why hiding a layer is a filter, not a delete. What a PDK actually contains The factory's package of layer names, rules, cells, and models — so your drawing tools speak the process. What is a photomask? The glass plate that prints a chip A photomask, also called a reticle, is a quartz plate with a chrome pattern. Light shines through it to copy one layer of a chip onto a wafer, and a chip needs a stack of them. What is a layout, really? Shapes, layers, units, and cells Not a picture of a chip: a file of integer coordinates on numbered layers, grouped into cells, that a factory turns into masks. What GDSII stores, why a screenshot is not a layout, and what to check before you send one. When the computer moves an edge Sizing moves every edge of a shape outward or inward by the same distance. Masks, solder openings, and rule checks depend on it, and corners, narrow necks, and unmerged pieces are where it surprises you. Who actually reads a layout? The same drawing is read by your eyes, a geometry checker, a connectivity check, a mask shop, and scripts that never see your colors. Why chip people live in microns Micrometers are the hallway unit for chip sizes; the file stores integer ticks, and a wrong unit silently resizes the chip. Why people write layout scripts Because a thousand polite rectangles should not be a career. Record, repeat, parameterize. Width and space The two oldest rules: don’t be skinny, don’t cuddle. Everything else is a variation.