Keepouts and blockages

A keepout or blockage is a region in a layout that is never manufactured. It tells a program which objects it may not put inside that region: a router may not run wires there, a placer may not put cells there, a fill generator may not add dummy metal there, or a board checker may not let two parts overlap there. The two words are used for the same idea. IC files and the LEF/DEF reference say blockage or obstruction; board tools say keepout, and KiCad now calls the object a rule area. A keepout has no electrical function. Its effect depends entirely on which program reads it and how that program was told to treat it.

The picture at the top is a LayoutEditor window with four SkyWater SKY130 standard-cell abstracts from the cell LEF file sky130_fd_sc_hd_merged.lef (OpenROAD test data), placed in two rows: dfxtp_1 and inv_1 in the lower row, ha_1 and mux2_1 flipped in the upper row. Gray outlines are the cell sizes. Dark teal rectangles are pin shapes on the local-interconnect layer li1, and the hatched blue bands are the metal 1 power-rail pins. Everything in amber is an li1 obstruction, the hatched orange strips are metal 1 obstructions, and the black squares are obstructions on the contact layer mcon. A router that receives these abstracts sees the amber, orange, and black areas as occupied and connects only to the teal and blue pin shapes. The inverter in the lower right has no obstruction at all.

Where a keepout is stored

A GDSII file has no record type for a keepout. A keepout is a shape on a layer/datatype pair that the process documentation reserves for that purpose; layer and datatype explains the pair. The SKY130 layer tables list a purpose named blockage and assign one pair per routing layer: li1 67:10, met1 68:10, met2 69:10, met3 70:10, met4 71:10, and met5 72:10. The description for each is "blockage layer used for IP integration (per CWR 137)", with DRC as the use. None of these pairs appears in the SKY130 mask-level list, which has its own numbers (metal 1 mask cmm1 36:0). The same table reserves areaid.op 81:54 for regions where automatic optical proximity correction is switched off. A drawn shape on 68:10 therefore reaches the foundry, if at all, as information for a check, not as chrome on a mask.

Keepouts exist in several families. Each family is read by a different program:

Family	What it keeps out	Where it is written	Read by
Routing blockage	wires and vias on one layer	LEF OBS, DEF BLOCKAGES with LAYER, SKY130 x:10 pairs	router, DRC
Placement blockage	standard cells	DEF BLOCKAGES with PLACEMENT, DEF component + HALO	placer
Fill blockage	dummy fill shapes	DEF BLOCKAGES with + FILLS, SKY130 waffle-drop pairs (cmm1 62:24), .ledrc fill(…, exclude=…)	fill generator
OPC exclusion	mask-data correction	SKY130 areaid.op 81:54	mask-data preparation
Courtyard	other components	KiCad F.CrtYd / B.CrtYd in the footprint	board DRC
Board rule area	tracks, vias, pads, zone fills, footprints	KiCad rule area on selected copper layers	interactive router, zone filler, board DRC

Other kits use other numbers: reading a layer map lists the GF180MCU place-and-route blockage on 34/5.

Obstructions in a cell abstract

A cell LEF describes each standard cell or block as an abstract: outline, pins, and obstructions; LEF and DEF in plain language introduces the file. The obstruction statement has this form (LEF/DEF 5.8 Language Reference, p. 136):

OBS
  LAYER met1 ;
    RECT 1.000 1.000 19.000 11.000 ;
  LAYER met2 ;
    RECT 1.000 1.000 19.000 4.000 ;
END

The reference defines OBS as "a set of obstructions (also called blockages) on the macro". The rules around it determine how a router treats a cell:

• A pin port overrules an obstruction. A metal 1 port inside a large metal 1 obstruction can still be reached by a via that lies entirely inside the port (p. 137).
• A router may reach such a port on the same layer if the path crosses the obstruction by less than the layer's minimum width plus minimum spacing (p. 137). Deeper inside, only a via from the layer above or below connects.
• The reference recommends combining small obstructions into one, for example the bounding box of all metal 1 in the cell, because simpler obstructions reduce routing time (p. 138). The same page asks that free metal 1 tracks stay accessible to the router, which limits how far rectangles can be merged.
• A non-rectangular block is described by its rectangular SIZE plus obstructions on a layer of type OVERLAP. Those shapes mark the part of the bounding box that no other macro may overlap (p. 139).
• OBS on a layer may carry EXCEPTPGNET, SPACING, or DESIGNRULEWIDTH, with the same meaning as the DEF options in the next section (p. 130).

In the SKY130 HD merged LEF, all 437 macros have an OBS block and 392 of them contain shapes. li1 obstructions occur in 391 macros, mcon obstructions in 103, and metal 1 obstructions in 101. The flip-flop dfxtp_1 in the lead figure (7.36 × 2.72 µm) has 43 li1, 6 mcon, and 14 metal 1 obstruction rectangles for five pins: D, Q, CLK, VGND, and VPWR. inv_1 has an empty OBS block: every li1 shape in its abstract belongs to the pins A and Y or to the rails, and its only metal 1 shapes are the two rail pins.

Blockages in a DEF

A DEF file describes one placed design. Its BLOCKAGES section holds keepouts that belong to the design rather than to a library cell (p. 232–236). This excerpt is part of the test file used below:

BLOCKAGES 3 ;
    - LAYER met1 + EXCEPTPGNET
        RECT ( 6000 6000 ) ( 9000 9000 ) ;
    - PLACEMENT + SOFT
        RECT ( 1380 5440 ) ( 3000 8160 ) ;
    - LAYER met2 + FILLS
        RECT ( 6000 6000 ) ( 9000 9000 ) ;
END BLOCKAGES

Coordinates are absolute and in DEF database units, here 1000 per micrometer. A LAYER blockage keeps routing out of one layer; on a cut layer it prevents vias. A PLACEMENT blockage keeps cells out of an area. The options change who obeys the blockage and when:

Option	Applies to	Effect (LEF/DEF 5.8, p. 233–235)
none	PLACEMENT	hard blockage: no cell is placed in the area
+ SOFT	PLACEMENT	only the initial placement avoids the area; timing optimization and clock-tree synthesis may place buffers there
+ PARTIAL maxDensity	PLACEMENT	initial placement fills at most maxDensity percent of the area with standard cells; value 0.0 to 100.0
+ EXCEPTPGNET	LAYER	blocks signal routing only; power and ground routing may enter, for example above a noise-sensitive block
+ FILLS	LAYER	no metal fill shapes in the area
+ SLOTS	LAYER	no slots in the area
+ COMPONENT name	both	the blockage belongs to a placed instance and moves with it
+ PUSHDOWN	both	the blockage was pushed down from the top level into the block
+ SPACING d	LAYER	other shapes keep distance d from the blockage; this value replaces all other spacing rules for it and may not exceed the layer's largest spacing value
+ DESIGNRULEWIDTH w	LAYER	the blockage counts as a shape of width w in spacing rules; not allowed at 20 nm and below

Two keepouts are written on the component itself rather than in BLOCKAGES. + HALO left bottom right top reserves a placement margin around a placed block, measured from its SIZE outline or from its merged OVERLAP shapes (p. 238). + ROUTEHALO distance minLayer maxLayer requires signal routes within that distance of the block edge to run perpendicular to the edge, which reduces coupling between the top-level wiring and the wiring inside the block (p. 242).

Keepouts on a circuit board

A board keepout comes in two forms. A courtyard belongs to a footprint: it is the outline of the space the part needs, and the board checker reports two overlapping courtyards (footprints are almost cells covers the footprint itself). The KiCad Library Convention (rule F5.3) draws it on F.CrtYd with 0.05 mm lines on a 0.01 mm grid and sets the clearance from the part body and pads to 0.25 mm by default, 0.15 mm for parts smaller than 1.5 mm, 0.5 mm for connectors, can-type capacitors, and crystals, and 1.0 mm for BGA and wafer-level packages.

A rule area belongs to the board. In KiCad 9 it is drawn on selected copper layers with five independent switches: keep out tracks, vias, pads, zone fills, and footprints. Tracks and vias cannot be routed into it, a copper zone does not fill it, and a pad or courtyard inside it is a DRC error.

Checking a keepout with .ledrc

LayoutEditor can check a drawn blockage like any other layer. The deck below reads SKY130 metal 1 drawing and the metal 1 blockage, then reports metal inside the blockage and metal too close to it:

units 1e-6
grid 0.005 um
mode flat

layer m1    = input(68, 20)   # met1 drawing
layer m1blk = input(68, 10)   # met1 blockage: no top-level met1 here

check "KO.1" "met1 inside the met1 blockage" : area(m1 & m1blk) > 0 um2
check "KO.2" "met1 closer than 0.14 um to the met1 blockage" : sep(m1, m1blk) < 0.14 um

The SKY130 rule tables give no numeric rule for the blockage layers. The halo distance in KO.2 is therefore a project decision. This deck uses the metal 1 minimum spacing m1.2, because the protected block may contain its own metal 1 up to the blockage edge.

The figure shows the six test cases in LayoutEditor with the deck's own markers in red, drawn 50 nm wider than reported so that a zero-width marker stays visible; where a marker covers a wire the overlap appears almost black. Each amber square is a 4 × 4 µm metal 1 blockage, and each blue line is a 0.14 µm wide metal 1 wire. Top row from left: A, a wire 1.000 µm above the blockage, passes; B, a wire across the blockage, gets a KO.1 marker; C, a wire 0.100 µm above the edge, gets a KO.2 marker in the gap. Bottom row: D, exactly 0.140 µm above the edge, passes because the rule is "less than"; E, a wire whose lower edge lies on the blockage edge, gets a KO.2 marker at distance 0; F, a wire entirely inside the blockage, gets a KO.1 marker.

The test script runs the deck on the same six cases (blockage 8 × 8 µm, same distances) and compares the markers per case with hand-counted values. The report lists rule, edge pair in database units (1 nm), and distance:

checks 2
errors 4
KO.1    20000,4000 28000,4000 | 20000,4140 28000,4140   0
KO.1    101000,3000 107000,3000 | 101000,3140 107000,3140   0
KO.2    48098,8100 39902,8100 | 40000,8000 48000,8000   100
KO.2    88140,8000 79860,8000 | 80000,8000 88000,8000   0

Both checks are needed. sep() measures the space between shapes and reports nothing for case B, where the wire and the blockage overlap. area(m1 & m1blk) reports nothing for case E, where the overlap has zero area. The run exits with code 1 because it found markers.

Keeping fill out

A fill generator adds dummy metal to raise the pattern density, as density is a rule too explains. A fill keepout tells it where not to do that. In .ledrc, the first argument of fill() is the region to fill, and exclude= is the keepout:

units 1e-6
mode flat

layer m1    = input(68, 20)
layer m1blk = input(68, 10)
layer frame = input(235, 4)

layer dummy = fill(frame, exclude=sized(m1, 0.3 um) | m1blk, shape=rect(0.5 um, 0.5 um), step=1.0 um)
output dummy 99, 0

check "FILL.KO" "dummy fill inside the met1 blockage" : area(dummy & m1blk) > 0 um2

The 0.5 µm squares, the 1.0 µm step, and the 0.3 µm distance to drawn metal are example values for this test, not SKY130 fill rules.

The test layout is a 20 × 20 µm frame on prBndry 235:4 with one metal 1 wire and an 8 × 8 µm metal 1 blockage. A 1.0 µm step gives 400 fill sites. The grown wire removes 19 of them. Without the blockage in exclude= (left), the fill places 381 dummies, and FILL.KO reports the 64 that lie inside the blockage, shown dark under their red markers. With the blockage in exclude= (right), 317 dummies remain and none is inside. The squares in the column at x = 14 µm and the row at y = 14 µm touch the blockage edge: exclude= removes fill that overlaps the keepout, not fill that abuts it. A distance to the keepout requires sized(m1blk, …) in the exclusion, in the same way as the 0.3 µm margin around the wire.

How keepouts get lost

A keepout works only while every program in the flow still sees it. The four cases below were measured in LayoutEditor, and the test script reproduces each one.

1. Wrong datatype in the deck. input(68) reads 68/0, not 68/10. With that line in place of input(68, 10), the deck above reports errors 0 and exits with code 0 on the same six cases. The run looks clean because the blockage layer is empty.
2. LEF obstructions after import. LayoutEditor reads OBS rectangles as ordinary boxes on the routing layer's number with datatype 0, the same as pin rectangles. On the test installation the macro above gave a metal 1 box on layer 68 and a metal 2 box on 69, next to the metal 2 pin box on 69; only the pin's text label A tells the pin from the obstruction. A converter that maps each LEF layer name to the drawing pair, as the script in LEF and DEF in plain language does, turns obstructions into drawing shapes. Such a GDS is a view of the abstract, not mask data.
3. DEF blockages after import. LayoutEditor skips the BLOCKAGES section with the message 1 BLOCKAGES are not supported under "Strong warnings". The count refers to the section; the test section held three blockages. No shape is created.
4. Blockage and drawing on one layer. With the default GDS setting, LayoutEditor loads 68/10 and 68/20 onto the same layer 68 and keeps the datatype per shape. Both are drawn in one color and switched on and off together, so on screen a blockage is easy to mistake for metal. With the setup option gdsAutoMapDatatypes, each pair is loaded onto a layer of its own. A script that selects shapes by layer number alone gets both pairs.

Checks before handoff

1. List the layer/datatype pairs in the file and confirm that each keepout family the flow relies on is present, for example 68:10 for a metal 1 blockage.
2. In every deck, read keepouts with input(layer, datatype) and run the deck once on a copy with one wire moved into the keepout; the run must report a marker.
3. After a LEF or DEF import, compare the obstruction and blockage counts in the source file with what the GDS contains, and read the import messages for skipped sections.
4. Confirm that the mask layer list contains no keepout pair.
5. On a board, run the DRC with courtyard and rule-area checks enabled and confirm that every footprint has a courtyard.