Density rules and fill: why empty space gets dummy shapes

A region of a chip can be almost full of one material or almost empty, and the factory cares which it is. Density rules put limits on that fraction, and fill (also called dummy shapes) is the geometry you add when a region is too empty.

The picture is a real cell row cut out of a layout. Gold vertical strips are poly gates, green and teal shapes are diffusion and the first wiring level, and the dark squares are contacts. The row itself is busy. The white band above and below it is not: on most layers nothing is drawn there. If a density window sat on that white band, its covered fraction would be close to zero, and that is the situation density rules exist to catch.

What density is

Density is the area of one layer inside a window, divided by the area of the window. A window 20 µm on a side has 400 µm². Shapes that add up to 280 µm² inside it give a density of 0.70; shapes that add up to 40 µm² give 0.10. A density rule states a minimum, a maximum, or both, and it states the window: its size and the step by which the window slides across the chip. Windows that step by less than their own size overlap, so a sparse corner is seen by several windows at once.

Real numbers make the idea concrete. The open SkyWater SKY130 rule manual checks metal pattern density in square windows of 700 µm × 700 µm that step across the die by 70 µm (rules m1.pd.2a and m1.pd.2b, repeated for metal2 to metal4). The same tables list a separate limit for the copper back-end option: at most 0.77 metal density in 50 µm windows stepped by 25 µm (m1.13, m1.14, m1.14a), together with a maximum metal width of 4 µm and a requirement to slot wide metal above 3.2 µm (m1.11, m1.12). Two processes from the same kit, two different window sizes. Never reuse another process's numbers; they belong to the process design kit you are drawing for.

Density can also be a limit on a single device rather than the whole chip. The SKY130 manual caps metal3 density over its vertical-parallel-plate capacitors at 0.25 (vpp.5a), because extra metal over a capacitor changes its value. A rule like that is the reason fill tools have keep-out layers.

Why the polisher cares

Most modern metal levels are made flat by chemical-mechanical polishing (CMP). The polishing pad presses on the whole wafer, and how fast it removes material depends on the pattern underneath. Over a wide empty field, the surface is removed faster and ends up lower; over a dense block it ends up higher. Wide metal lines dish in the middle, and dense arrays of lines erode as a group. The result is metal and insulator thickness that change with the neighborhood: a wire in a sparse region comes out thinner and more resistive than the same wire in a dense region, and the next layer is built on a surface that is not flat. Etch has a related effect, usually called loading, where the local amount of exposed material changes how fast it etches. A maximum density protects against the opposite extreme: large solid regions that dish or that the deposition and etch steps cannot handle evenly.

Density rules turn these process effects into a number a checker can measure. The SKY130 rule table lists m1.pd.1 as a recommended minimum oxide pattern density of 0.7 for the aluminum back end, measured in the 700 µm windows stepped by 70 µm described above. In LayoutEditor's rule-file language, .ledrc, a simplified teaching version of that rule is a single check line:

units 1e-6
layer m1 = input(68, 20)
check "m1.pd.1" "m1.pd.1 : met1 density >= 0.70, 700 um window, 70 um step" : density(m1, window=700 um, step=70 um) < 0.70

units 1e-6 makes a bare number mean micrometers. input(68, 20) reads metal1 drawing, which SKY130 keeps on GDS layer 68, datatype 20. density(…) slides the window across the cell, and every window whose covered fraction is below 0.70 becomes a marker. From a shell, layout --drc m1_pd.ledrc design.gds --outdir=drc_out runs it and writes a report and a marker file.

This deck is a simplification, not the foundry check. The 0.7 in the table applies to a mask-level layer the foundry derives from the drawn metal, not to the drawn shapes themselves; the table notes that the check is part of the foundry's own mask-data processing and may not be checked by DRC; and the companion metal1 rule grades the threshold by how much of the window is covered by generated fill and skips cells smaller than 40,000 µm². Public shuttle checks for SKY130 also size the metal before measuring the 700 µm windows, and separately cap the metal that may cover the whole project area. Use the deck to learn how a windowed density check behaves, and use your foundry's or shuttle's own deck for sign-off.

To see the check work, it was run on a test layout of 1400 µm × 700 µm whose left half is 75% metal and whose right half is 30% metal, drawn as vertical stripes on a 10 µm pitch. It marks 180 windows, and the count can be checked by hand. Windows start every 70 µm in both directions: 20 positions across and 10 up. Windows that would stick out past the edge of the layout are cut off at the edge, so the narrow ones on the right see only the sparse half. Only the first two positions across pass, at 0.75 and 0.705; every window further right takes in more of the 30% half and falls below 0.70. Eighteen failing positions times ten rows is 180. The same layout with 75% metal everywhere gives no markers. Every sign-off DRC tool has an equivalent of this check.

Fill: shapes that are not the circuit

The second picture is the standard repair for a window that is too empty. The two navy wires are the circuit. The gold squares are fill: small, regular shapes on the same layer, placed in the open field so the covered fraction rises into the allowed range. Each square keeps a gap to the wires. That gap must meet at least the spacing rule, and fill tools usually apply a larger keep-out than the minimum, because a square that is close to a wire is still metal on the same layer.

Fill is generated, not drawn by hand. A fill pass looks for regions where coverage is low, subtracts keep-out zones around real shapes (and around anything marked as sensitive), and tiles the rest. Foundry kits often ship their own fill scripts and keep the generated fill on a separate layer purpose, so it can be told apart from real wiring. SKY130 calls its generated metal fill "waffle drop" (cmm1 for metal1), and its metal1 table spells out a graded check: if waffle drop covers an entire 700 µm window, metal density below 70% is flagged; if it covers 80–100% of the window, below 65%; at 60–80% coverage, below 60%.

The third picture is the other end of the scale: a region where almost every layer covers most of the area. A window here would never need fill, and on some layers it can approach a maximum density limit. When a window is too full, the repair is to remove metal that is not part of a net, to slot wide straps (the copper rules above require it), or to spread the shapes out — never to delete wires to reach a number.

Filling a layout in LayoutEditor

LayoutEditor has a fill tool of its own, the Density Fill... command. Its dialog asks for the layer to fill, the target density, and the minimum distances: how wide each dummy shape must be, how far dummies stay apart, and how far they stay from shapes that are already drawn. The same function is available from Python through LayoutScript, LayoutEditor's scripting interface, which makes the run repeatable. This script builds a small test cell and fills it:

from LayoutScript import project

um = 1000                                  # 1 database unit = 1 nm
layout = project.newLayout()
drawing = layout.drawing
cell = drawing.currentCell
cell.cellName = "FILLTEST"

cell.addBox(0, 0, 40*um, 40*um, 235)       # frame on a spare layer: sets the fill area
for x, y in [(3, 3), (23, 3), (3, 23), (23, 23)]:
    cell.addBox(x*um, y*um, 4*um, 10*um, 68).setDatatype(20)   # drawn met1, 10 % per window

drawing.deselectAll()
# layer, target density %, gap to drawn shapes, min width, min space, window size, grid
drawing.densityFill(68, 35, 300, 500, 300, 20*um, 5)
drawing.saveFile("filltest_35.gds")

The test cell is a 40 µm square with one 4 µm × 10 µm metal1 bar in each 20 µm quarter, so every quarter starts at 40 µm² of metal in 400 µm², a density of 10%. densityFill takes the layer number, the target in percent, and then lengths in database units, which are nanometers here: dummies stay 0.3 µm away from drawn metal, are at least 0.5 µm wide, keep 0.3 µm between each other, and the density is evaluated in 20 µm windows on a 5 nm grid. The target counts everything on the layer, drawn metal and dummies together. The new shapes land on datatype 0 of layer 68, so they stay distinguishable from the drawn metal on datatype 20.

The fourth picture is the saved result, drawn in LayoutEditor. The navy bars are the drawn metal1, the gold stripes are the 56 dummy shapes the fill added, and the thin dark lines mark the frame and the four 20 µm windows (they are drawn for the picture, not part of the layout). Most dummies are 0.5 µm wide stripes, they stop 0.3 µm short of each bar, and a short, slightly wider piece near the top corner of each window trims the total to the target. Measured from the saved file, the metal1 area inside each window is 140 µm² of 400 µm², or 35.00%, in all four windows. The same cell filled to 25% and to 50% measures 25.00% and 50.00% in every window.

On a small design, the frame decides what the density means. densityFill lays its windows over the extent of the cell, and the 40 µm box on spare layer 235 is there to pin that extent. Without the box, the windows are laid around the drawn bars instead. In the same test with 20 µm windows, the dummies then spread up to 4.85 µm beyond the bars, into space the frame would have kept empty. With 30 µm windows and no frame, the fill reached 35.0% inside its single 30 µm window, but the same metal measured over the 40 µm square is only 19.7%. A density number is only meaningful together with the area it was measured over, so draw the frame the way the factory will measure: the die outline, or the boundary of the block you deliver.

Whatever made the fill, check it with a separate pass. This .ledrc deck reads the drawn metal and the dummies back from the saved file and checks the dummy sizes, the gaps, and the density in each 20 µm window against a minimum of 0.20:

units 1e-6
layer m1    = input(68, 20)                 # drawn met1
layer dummy = input(68, 0)                  # shapes added by densityFill
layer all   = m1 | dummy
check "fill.w"  "dummy width >= 0.5 um"          : width(dummy) < 0.5 um
check "fill.s"  "dummy to dummy space >= 0.3 um" : space(dummy) < 0.3 um
check "fill.sm" "dummy to met1 space >= 0.3 um"  : sep(dummy, m1) < 0.3 um
check "fill.d"  "met1 density >= 0.20 per 20 um window" : density(all, window=20 um, step=20 um) < 0.20

m1 | dummy merges both datatypes into one layer before the density is measured, and sep(dummy, m1) measures the gap between the two layers. On the cells filled to 25%, 35%, and 50%, the deck reports no markers. On the same cell before fill, fill.d marks all four windows, each at 10%.

The rule-file language can also generate fill itself, which makes a useful second opinion:

units 1e-6
layer m1   = input(68, 20)
layer area = input(235, 0)
layer dummy = fill(area, exclude=sized(m1, 0.3 um), shape=rect(0.5 um, 0.5 um), step=0.8 um, density=0.25)
output dummy 68, 0

fill(…) tiles the frame region with 0.5 µm squares on a 0.8 µm pitch, keeps out of the drawn metal grown by 0.3 µm, and output dummy 68, 0 writes the result to layer 68, datatype 0. The two tools read a density target differently. In fill, density=0.25 counts only the new dummies, so on the 10% test cell it adds 400 µm² of squares (1,600 of them), and the layer ends at 35.0% overall. Without a window= setting, fill places squares in raster order until the global total is reached, so on this cell two windows end at 42.9% and two at 27.1%. Adding window=20 um caps the dummies at 25% in each window, at the cost of a much longer run. densityFill, by contrast, aims at the total density of the layer in each window.

What fill costs

Fill is not free. Every fill square is a conductor near your wires, so it adds coupling capacitance, which slows signals and can couple noise. Floating fill (not tied to any net) and grounded fill behave differently electrically, and kits say which they allow. For analog circuits, fill can upset matching: a dummy shape on one side of a matched pair is a new neighbor that the other side does not have. That is why sensitive nets get wider keep-outs, why matched structures get symmetric fill or none, and why device-level rules like the SKY130 capacitor limit exist.

Hiding fill is useful when you trace connectivity, because it leaves only the conductor you care about. It is the wrong state to send to the mask shop: without the fill, the window around the route is mostly empty, and the polish step treats it that way. Hide fill for review, keep it in the data.

Three mistakes account for most fill problems. A fill square overlaps a wire after the wire was moved, and becomes part of the net — the wire is now wider, or shorted to a neighbor. Fill is placed on a scratch layer that the factory never builds, so it fixes nothing. Or fill was generated before the last routing change and never regenerated. The habit that prevents all three: regenerate fill after every routing change, keep it in its own cell or layer purpose, and run DRC after fill, not only before.

PCB design has the same instinct at a larger scale. Board fabricators ask for balanced copper across layers, and designers add copper pours or "thieving" patterns to sparse areas so plating is even and the board does not warp. The geometry is coarser, the reason is the same: the process behaves best when every region looks a little like every other region.

To check a window by hand, pick a square, add the area of the layer inside it, and divide by the square's area. If the fraction is below the minimum, fill the open field and divide again. Then measure the gap from the nearest fill square to the nearest wire against the spacing rule. A quiet window can be illegal, and fill that touches a wire is a different violation.