Optical proximity correction (OPC)

Optical proximity correction, or OPC, is a step after layout that changes the shapes on a photomask so that the pattern printed on the wafer matches the drawn layout. It is needed because the printed image deviates from the mask at small dimensions. Take a straight line with square ends, 180 nanometers (nm) wide and 1.6 micrometers long. In the layout it is a rectangle with four sharp corners. In the factory it is printed by projecting light through a glass plate, and at this size the optical image cannot reproduce sharp corners. The mask therefore cannot be an exact copy of the drawing. OPC reshapes the mask pattern so that the printed result lands on the drawn intent.

The picture is a LayoutEditor window with a teaching layout, not a cell from a real product. The black outlines are the drawn shapes: an L-shaped line on the left and an isolated straight line on the right, both drawn at that width. The amber shapes are the same lines after correction, the pattern that would go onto the photomask. Square extensions stick out at every line end and every outer corner. At the inner corner of the L, a small square is removed. Next to the isolated line are two thin amber bars that touch nothing. None of these additions is meant to print as a separate shape; they only change how the optical image forms. The layer list on the left stores the two versions as separate data: "drawn intent" and "mask after OPC".

Why it matters

Lithography projects the mask image onto a light-sensitive film, the photoresist, on a silicon wafer. Light passing a small opening diffracts. Production exposure has long used deep ultraviolet light with a wavelength of 248 or 193 nm, so the drawn line is about one wavelength wide, and the image on the wafer is a blurred copy of the mask. The resist reacts wherever the intensity exceeds a threshold, and a blurred shape cut at a threshold does not have the drawn outline.

The second picture shows the effect with a deliberately simple printer model. Five lines are drawn in black, each 180 nm wide: three packed lines with gaps of the same size, the L, and an isolated line on the right. Teal is the print after the drawing is blurred and cut at half intensity. Three effects appear:

• Line-end shortening (pullback): every line end prints short, here by about 75 nm at each end.
• Corner rounding: the outer corner of the L is cut off on a curve about 80 nm inside the drawn corner, and the inner corner fills in.
• Iso-dense bias: the packed lines print about 185 nm wide, because diffracted light from the neighboring lines adds to their own intensity. The isolated line receives no such contribution and prints about 160 nm wide.

Iso-dense bias is one form of the proximity effect, and the effect gives OPC its name: the required correction depends on the geometry in the proximity.

These deviations affect function. A line end usually has to land on a contact, a via, or the far side of a transistor. If it prints short, the overlap shrinks and the resistance of that connection rises. One study of the problem notes that a line can meet its width specification and still be an unacceptable pattern because its ends pulled back. A transistor gate that prints narrower or wider than drawn switches at a different speed and has a different leakage. A 1999 design-automation paper described the change as the end of "what you see is what you get": the drawing no longer matches the mask, and the mask no longer matches the silicon.

How it works

Pre-distorting the mask

OPC changes the mask, not the circuit. It lengthens a line end that prints short, adds material at a corner that rounds, and widens an isolated line that prints thin. Researchers describe the task as an inverse problem: given the target pattern on the wafer, find the mask whose print comes closest to it. No exact solution exists, because no mask makes the optics print a truly sharp corner. The goal is every edge within tolerance.

Correction types

Each correction type has a name, and the lead picture contains each of them:

• Serif: a small square added at an outer corner to reduce rounding.
• Anti-serif: a square removed from an inner corner to reduce fill-in; it is the missing square at the inner corner of the L.
• Hammerhead: a line end made wider and longer against pullback; in the lead picture, the two extensions at each line end together form one hammerhead.
• Bias: an entire edge moved outward or inward.
• Notch: a local reduction of line width.

Bias and notch correct width errors along a line.

The thin free-standing bars are sub-resolution assist features (SRAFs), also called scattering bars or outriggers. They are placed next to an isolated line so that its optical surroundings resemble those of a dense array. A 2003 lithography column states that their main purpose is to make an isolated line respond to focus errors the way a dense line does, not only to correct its width. Their one strict requirement is that they never print. They are therefore made as large as possible while still not printing anywhere in the factory's range of focus and exposure. Where two lines are too close for a bar to fit between them, only a bias can be applied.

Rule-based and model-based OPC

There are two methods to determine the corrections. Rule-based OPC uses a lookup table: for a given line width and neighbor distance, move the edge by a given amount; add an extension of a given size at every line end. The rules come from experiments or simulations, and a program applies them wherever the configuration occurs. The method is fast.

Model-based OPC simulates the print. The program divides every edge into short segments called fragments, each with an evaluation point. It simulates the image, measures at each evaluation point the distance between the printed edge and the drawn edge (the edge placement error), and moves each fragment to reduce that error. It then simulates again and repeats. The model must be calibrated against real wafers and recalibrated when the process changes. Runs are slow, but the method handles shapes that no table anticipated. One university lithography course states that rule tables alone are no longer accurate enough below about 180 nm designs, and that chips at and below the 250 nm generation need OPC at all. These limits are one course's guidance, not a fixed threshold.

A model-based run on the example

The third picture shows the same five lines after a small model-based run with the same simple model. The black outlines are the drawing; the amber outlines are the corrected mask. Results of the run:

• Edges divided into 240 fragments.
• After about a dozen simulate-and-move iterations, the typical edge error fell from about 65 nm to about 5 nm.
• Two assist bars, 60 nm wide and 200 nm from the isolated line, were placed first by a fixed rule.
• The new print (teal) fills the black outlines: packed and isolated lines both print at about 179 nm, line ends land within about 12 nm of the drawn ends, and the outer corner of the L lies within about 20 nm of the drawn corner.
• The assist bars alone widened the isolated line from 160 to 171 nm. The peak intensity under a bar stayed at about half the printing threshold, so the bars do not print.

The model is a blur followed by a threshold, which a 1998 dissertation on OPC calls a naive resist model. Production models add diffraction, resist development, and etch bias. The numbers demonstrate the mechanism, not any factory's process.

Where it sits in the flow

OPC is not part of the drawing. The 1999 paper places it as a post-processing step during physical verification or mask preparation. The layout, saved in a format such as GDSII, is the intent. OPC turns it into corrected mask data. Fracture then divides that data into the simple figures a mask writer can expose, as described in mask fracture in one sitting. The writer produces the photomask, and a stepper projects its image onto the wafer. Each file is derived from the previous one. When the circuit changes, the intent is edited and the correction is run again.

Designers have not always left corrections to software: for very dense chips, engineers added serifs by hand, by trial and error, as early as the 1970s, until automation took over. Traces of the step also appear in an open process kit. The SkyWater SKY130 rules, for a 130 nm process, list a mask layer marked as an OPC layer among the layers whose mask data uses a finer grid, and they mark some rules "DNF", drawn not equal final, where the size on silicon differs from the drawn size. These entries indicate downstream processing; they do not describe that factory's correction flow.

Why corrected files grow

Every moved fragment adds vertices. In the example, the five drawn lines have 22 corners in total; the corrected mask, including the two bars, has 350, about sixteen times as many, for short and simple lines. Researchers track this as the data expansion factor: file size after correction divided by file size before. The growth increases the time to transfer the data, write the mask, and inspect it, and an inspection tool can flag a complex correction as a defect.

OPC also affects hierarchy. A layout file saves space by defining a cell once and placing it many times. OPC depends on neighboring geometry, and a cell's neighbors differ between placements; assist bars may also fall outside the cell boundary. Placements that were identical then need different corrections. This is one reason corrected data grows so much, and why compact formats matter for it, as OASIS vs GDSII explains.

A common mix-up

A frequent misconception is that OPC makes the chip match the screen. The 1999 paper states the opposite: the purpose of OPC is not to make the manufactured structure match the on-screen geometry in the layout editor, but to make the manufactured circuit work like the designed one, with no more correction than that requires. A rounded corner on a plain wire is acceptable; a drift in transistor gate width is not.

A second misconception is that a careful designer should draw the extensions. Extra jogs and serifs on a design layer are treated by the correction step as part of the intent and are corrected again. They also cause violations in the checks that measure the drawing. If a special device needs hand-shaped corrections, this has to be agreed with the process owner, as in nanoscale work; it is not a routine practice.

Things that go wrong

• An oversized assist bar prints as a real line: an unintended resist sliver.
• Corrections on two close neighbors can merge on the mask. The example run kept corrected shapes at least 80 nm apart, a simplified substitute for the mask maker's own spacing limits.
• At some spacings the lines are too far apart to behave as a dense array and too close for an assist bar. Only a bias remains, and the print is sensitive to focus drift.
• The mask writer does not reproduce small extensions exactly, so the mask itself rounds them slightly.
• A classic process error: someone patches the corrected or fractured file to fix a problem, and the next design change, which starts again from the intent, discards the patch without notice.

In software

In LayoutEditor, as in any layout editor, you draw the intent: clean shapes on the correct layers that follow the design rules of the process kit. Rules such as the required line extension past a contact or the minimum distance between two facing line ends are set with these printing limits in mind. The correction itself runs later, during mask data preparation, with models and rule tables owned by the factory.

The figures on this page keep that separation: every outline is a real LayoutEditor polygon, while the corrections and prints come from a small blur-and-threshold program. The program is a simplified model, but it runs the same simulate-and-move loop.