PDK

The kit a foundry or a board house gives you: sheet names, rules, device recipes, and example drawings, so your work matches their factory.

That kit is a PDK, a process design kit. A layout person cares because a layer number without a PDK is a rumor. The kit says metal 1 is layer 31 datatype 0, minimum width 0.14 micrometer, and here is the PCell for an nMOS. DRC and LVS decks live here. So do tech files and sometimes LEF.

You would see this as a directory tree: tech, cells, rules, models. Open a new library “on the 180 nm PDK” and the layer list populates. A student run without a PDK is a guess plus email.

A PDK is not a GDSII chip. It is the dictionary and the furniture catalog. A library of standard cells or footprints may ship beside it or inside it. Typical views include full layout, abstract place-and-route data, timing tables, and simulation netlists — each for a different job.

A common mix-up is mixing two PDKs in one file because a via cell looked handy. Layer 31 in kit A is not layer 31 in kit B. The mask shop will not merge your optimism.

A PDK also ships models, display resources, and sometimes a tutorial cell. You would see a layer map, a design-rule manual, and a DRC directory. Pin the version in the project: pdk-180-rev4. Mixing rev4 devices with a rev3 rule deck is a classic tapeout scare. Board houses ship a thinner cousin: a stackup plus a footprint library. Photonic kits keep the same social structure with optical building blocks; MEMS work often leans on a handbook more than a full CMOS-style kit.

Read more in what a PDK actually contains, design rules and DRC, and what a layer is for.