LVS

LVS (layout versus schematic) is a program that extracts devices and wires from a layout drawing and checks whether they match the circuit the designer said they wanted.

The left gate has a plug under the metal. The right gate has no plug, so the metal does not meet that side.

A clean geometry check can still hide a swapped pin or a missing via, so LVS is the connection check that runs beside the geometry spellchecker DRC. Both run before tapeout. DRC asks whether every width is legal. LVS asks whether the names and connections match. It reads a netlist from the schematic, or from synthesis, and builds another netlist from the drawn layers: active, poly, metal, and the cuts that join them. Then it compares the two lists. The extraction needs a correct layer map in the PDK. On a board, the same question is whether the copper matches the schematic, often under a different product name.

A report might read 128 nets matched, 2 unmatched, device count 4096 vs 4098. A short between vdd and out is an LVS error even when every width is legal. A spare dummy transistor can appear as an extra device that the comparison must filter. Renaming nets in the layout until the report goes quiet, without fixing the schematic, silences the reporter and leaves the product wrong. Why the two lists exist and how to walk the comparison is LVS: layout versus schematic. The geometry check that can still pass while this one fails is DRC is a spellchecker.