Netlist

A netlist is a list of devices and named connections, with no pictures: what exists, and what touches what.

Three symbols and the two wires that tie them. The list of that tying has no picture of its own; this is the circuit the list names.

Tools speak lists when they are serious. Synthesis writes a gate netlist. A schematic export writes one. LVS builds another from geometry and compares. A short is two names that became one. An open is one name that became two. The text can look like NAND2 U12 (.A(n1), .B(n2), .Y(out)), or like a SPICE deck with M1 d g s b nch w=2u l=0.18u. A thousand lines is a small block. A million is a chip.

The pictures that must match the list are the schematic and the layout. The net names are the spine. DEF can carry a placed netlist plus routes. A PDK supplies the device names the list is allowed to use. Editing the layout until it looks wired, and never updating the netlist the checker reads, leaves the comparison looking at files, not hopes. LVS compares those files.

Netlists come in dialects: Verilog, SPICE, EDIF, and tool-private lists. The idea stays the same. A synthesis netlist may carry INVX1 instances while a schematic netlist carries M1 transistors. LVS must be told how those names map. A stale netlist is worse than none, because the checker will bless last week's circuit. Date the file next to the stream. How the name list and the drawing are supposed to agree is LVS: layout versus schematic. The drawing itself is what is a layout. A netlist that matches can still sit on illegal geometry, which is design rules and DRC.