Net

A net is a named electrical or logical connection: every piece of conductor that must stay at the same voltage.

Geometry is not the circuit until someone labels it. A schematic net named clk should become a tree of metal and via cuts that extract back to clk. If two shapes touch and carry different names, the result is a short. If they should touch and do not, the result is an open. Highlight vdd and a red tree lights up across the chip, perhaps 40 millimeters of strap and a thousand vias. The netlist listed vdd as one node. The drawing must agree.

A strap joins the left landing to the middle one. The right landing is the same kind of square and is not joined.

A pin is where a net meets the outside of a cell. LVS is the check that the extracted nets match the schematic. A board net is the same idea on copper. Overlapping metal is the shape people treat as a net before any check has run. Without connectivity extraction, that overlap is a picture. Names and cuts make the net. Whether those names match the schematic is LVS: layout versus schematic. The cut between two metals is vias and contacts. The sheets the shapes sit on are what is a layout.