Footprints are almost cells

You want the same eight-pin chip in six places on a circuit board, and you do not want to draw its eight copper pads six times over.

So you draw the landing site once: the copper pads the leads will be soldered to, plus the marks that tell people and machines how the part sits. Board designers call that drawing a footprint, or a land pattern (a "land" is the standards word for a pad). Every time you drop it onto the board you make a placement. Chip designers have the same idea under other names: the drawing is a cell, each stamp is an instance. The picture at the top of this page is that idea with real geometry from a layout editor: one board, six placements of one small-outline eight-pin footprint, some turned 90 or 180 degrees. Each site shows the same eight copper pads, the same white outline and pin-1 dot, and the same yellow rectangle around it. Only position and rotation change, and the small round vias and the traces beside the pads belong to the board, not to the footprint.

Why it matters

A footprint is the most reused drawing on a board, so a mistake in it is the most repeated mistake on the board. A pad that is too short repeats at every site. A pin-1 corner on the wrong side repeats at every site. When a board comes back with every regulator soldered backwards, it is rarely six separate errors. It is one master placed six times.

The first thing a footprint must get right is the pads against the part. Open the empty land pattern before you look at a package sitting on it.

That photograph shows such a site before assembly: rows of bare copper lands on all four sides of an empty square of green solder mask, and a white corner mark at lower left. Check four numbers against the part drawing in the datasheet: how many pads, the pitch (center-to-center spacing), the length and width of each pad, and the span from one row to the opposite row. Get the span wrong and every lead lands on the edge of its pad. Make a pad too small and the joint is starved of solder. Make it much too large and the molten solder can pull the part sideways before it freezes.

Board designers rarely invent these sizes. The IPC-7351 land-pattern standard derives pad sizes from the part's dimensions and tolerances and offers three variants of each pattern: most, nominal, and least material, for roomy, average, and dense boards. The same standard defines a courtyard, the keep-out rectangle around the part that no other part may enter. It extends 0.50, 0.25, or 0.10 millimeter beyond the outermost pad or body edge for those three variants. A footprint copied from somebody else's library carries their choice of variant whether you noticed it or not.

How it works

A footprint looks like one drawing, but it is several drawings on several layers that must agree, plus a reference point.

That figure is a single master placed six times in LayoutEditor, with pad numbers turned on so you can follow the pins. Look at the top-left site first, the master as drawn. The copper-colored rectangles are the copper lands. The thin pale outline around each land is the solder-mask opening: the window in the green coating where copper stays bare, usually a few hundredths of a millimeter larger than the land on each side. The dark crosshatch inside each land is the paste aperture: the hole in the stencil that prints solder paste onto the land before the part is placed, often the same size as the land or a little smaller. The white bars and the white dot are silkscreen, ink printed on the board for humans, with the dot beside pin 1. The yellow rectangle is the courtyard. The lighter green block in the middle is the package body as an assembly outline.

Here are real numbers for that part. Under the IPC naming scheme its footprint is called SOIC127P600X175-8N: small-outline integrated circuit, 1.27 mm pitch, 6.00 mm lead span, 1.75 mm maximum height, 8 pins, nominal variant. A nominal land pattern for it uses pads roughly 1.55 mm long and 0.60 mm wide whose centers sit 5.40 mm apart, row to row. The name encodes the geometry, so two footprints with the same full name should have the same lands.

The paste layer has its own physics. Paste only leaves the stencil cleanly when the opening is large compared with the metal wall around it. Stencil guidelines express that as the area ratio: the area of the opening divided by the area of its walls. For a rectangular opening of length L and width W in a stencil of thickness T, that is L·W / (2(L + W)·T). A rule of thumb is to stay at or above 0.66. A 1.45 × 0.50 mm opening in a 0.125 mm stencil gives about 1.49, which is easy. A 0.25 mm square opening in the same stencil gives exactly 0.50, and paste tends to stay in the hole. That is why paste apertures are a separate layer of the footprint and not an automatic copy of the copper.

Every footprint also has an origin, usually the center of the package body, and a zero orientation. IPC-7351 puts pin 1 at the upper left for small-outline packages like this one, as in the top-left site. When the board is finished, the design tool writes a placement list (often called a pick-and-place or centroid file) with one line per part: its name, the X and Y of its origin, its rotation, and its side. The assembly machine trusts that list. If the origin in the master is off by half a millimeter, every placement of that footprint is off by half a millimeter in the same direction.

Now read the top row of the figure from left to right: rotated 0, 90, and 180 degrees. Follow pins 1 to 8 and they always run counterclockwise around the part. Rotation never changes the pin order. The bottom row holds the same three rotations, each mirrored, and there the pins run clockwise. A mirrored footprint is a different footprint. On the top side of a board, the bottom row would put every pin on the wrong pad.

Almost a cell, not quite

In a chip layout file such as GDSII, a placed cell is a live reference. The file holds one definition, and every instance points to it. Edit the definition and every instance changes the next time anything looks at the file.

Many board tools work differently. KiCad, for example, keeps footprints in libraries, but the board file stores its own copy of every placed footprint together with the library name it came from. Edit the library footprint and the board does not change until you run the command that updates footprints from the library. Edit one placement on the board and only that placement changes. That design protects board-specific edits, but it means a placement is a copy with a name tag, not a pure reference. Treat the library footprint as the master anyway. If one site truly must differ, save a second footprint under a second name and place that name, so the exception stays visible.

At manufacturing time the hierarchy disappears. Gerber, the plot format board fabs read, describes one layer per file as a flat picture: every pad is written out where it lands, with no footprints left to edit. LayoutEditor's documentation says the same about its own export: a Gerber file cannot hold hierarchy, so a flat copy of the design is saved, one file per layer. Newer Gerber versions can attach the footprint name, rotation, and pin positions to each part as labels for assembly, and the ODB++ and IPC-2581 formats carry component and package data in one structured package. In every case, the editable master lives in your design data, not in the plot.

A common mix-up

Datasheets draw packages from more than one side, and beginners copy the wrong one. A top view looks down on the part as it sits on the board, as if the body were transparent. That is the view a footprint is drawn in, because board editors also look down on the top of the board. A bottom view looks up at the leads or solder balls, and it is the mirror image. Copy a bottom-view pin map straight into a footprint and you get the bottom row of the figure above: pin 1 in the wrong corner and every pin in reverse order. This mistake is especially common with ball-grid-array parts, whose ball maps are often printed bottom-up.

The opposite surprise is harmless. When you move a part to the underside of the board, the design tool mirrors the whole footprint and moves its copper, mask, paste, and silkscreen to the back-side layers. Seen from above, through the board, its pins now run clockwise. That is correct: the part really is upside down.

Things that go wrong

The schematic symbol and the footprint must agree on pin numbers, because the netlist, the list of connections drawn in the schematic, connects symbol pin 3 to pad 3 and nothing else. Small transistors in the three-pin SOT-23 package are the classic trap: the package outline is standard, but different parts assign base, emitter, and collector to pads 1, 2, and 3 differently. The same footprint name is not proof of the same pinout. This check is the board world's small version of LVS, the comparison chip designers run between layout and schematic.

Pitches that almost match are another trap. A part with 0.65 mm pitch on a footprint drawn at 0.635 mm looks right for the first few pins, and by the tenth pin in a row the lead has drifted 0.135 mm off center. Check the outermost pad on each row against the drawing, not the first.

A large exposed pad under a package, used for heat, needs its own paste plan. Paste printed across the whole pad can float the part on a pool of solder, so that pad's paste is often split into several smaller windows that together cover only part of it.

Before the first board is ordered, print the footprint at 1:1 scale, pads only, and set the real part on the paper in the orientation the assembly drawing shows. Touch the pin-1 mark on the body, then the pad the silkscreen calls pin 1. If those are opposite corners, fix the master, not the placement. A pencil mark on paper is the cheapest place to find a mirrored footprint. A soldered board is the most expensive.

In LayoutEditor

LayoutEditor treats a footprint as what it almost is: a cell. Draw the lands, mask openings, paste apertures, silkscreen, and courtyard on named layers in one cell, give it the package name, and place it on the board as cell references with whatever rotation or mirroring each site needs. The figures on this page were built exactly that way, so the six placements share one definition in the saved layout file. When a board shop needs Gerber, LayoutEditor writes each used layer to its own flat file, and the master cell stays intact in your design data for the next revision.