Chip tutorial 5: DEF to GDS and DRC in LayoutEditor

You want the routed encoder turned into a GDSII file a layout tool can check.

Without the sky130 standard-cell library merged in, the placement file (DEF) stays hollow: fill, decap, and tap are empty outlines, and a design-rule run on that picture is lying about geometry you do not have. In the DEF header, UNITS DISTANCE MICRONS 1000 means 1000 database units are one micrometer, so the integer 95000 is 95 micrometers on a side, not 95 millimeters and not 95 nanometers. After import, reference origins land on a 5.44 micrometer grid, twice the 2.72 micrometer site height, because every second row is flipped and a flipped cell reference sits with its origin on the top edge of its row. Read the ROW lines in the DEF text before you blame the placer. The teaching GDS is here. The routed DEF that goes with it is here; the Part 4 zip holds the OpenROAD script that produces one, not a finished file. Streaming polygons does not re-prove the counter. That remains a simulation job.

DEF and the cell library go into LayoutEditor. A GDS stream and a rule check come out.

Hollow names versus a stream you can measure

DEF says where cells and wires sit, in LEF vocabulary: die outline, rows, placed components, pins, nets, and routing. LEF abstracts are a bounding box, pins, and a routing obstruction. They are enough for a placer and not enough for a mask shop. GDSII stores numbered layers, polygons, and a cell hierarchy. Names such as met1 bind to layer and datatype pairs through the PDK setup. Guessing colors in the window is not a map.

The import order is TechLEF, then the cell LEF, then sky130_fd_sc_hd.gds, then the routed 95 micrometer DEF, then save the top cell encoder_top. Skip the cell GDS and the screenshots look empty.

Left: the words CELL and FILL inside an empty frame. That panel is labels, not mask polygons, and a rule check on it is misleading. Right: a teaching sketch of a route, standing in for the merge. The filled rows you actually measure are the LayoutEditor windows below, after sky130_fd_sc_hd.gds has been imported.

On your machine, set PDK_ROOT to the directory that contains sky130A and PDK to sky130A. Useful files under that tree are the HD tech LEF, sky130_fd_sc_hd.lef, sky130_fd_sc_hd.gds, and the LayoutEditor layer macros in libs.tech/LayoutEditor/. Run the layer macro before you open the DEF. An empty map is a quiet, wrong coloring.

A portable macro then opens the tech LEF, imports the cell LEF, imports the cell GDS, imports the routed DEF, sets the cell to encoder_top, and saves encoder_top.gds. Afterward, file encoder_top.gds should report a GDSII stream, often version 7, on the order of a few megabytes for this teaching die.

95000 is 95 micrometers

DESIGN encoder_top ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 95000 95000 ) ;

One database unit is one nanometer. Treating the DEF integers as micrometers builds a 95 millimeter "chip." Saving GDS with the wrong database unit shrinks or inflates everything by a thousand.

The integer 95000, at 1000 units per micrometer, beside a 95 micrometer scale. Read the scale bar in the editor against that pair before you trust a zoom level.

The sky130 HD site unithd is 0.46 micrometers wide and 2.72 micrometers tall, so a correct DEF row pitch is 2.72 micrometers. In the merged GDS the cell bodies tile at exactly that pitch. What sits on a 5.44 micrometer grid is the reference origin, not the row. The DEF alternates N and FS rows. A DEF point names the lower left corner of the placed cell's box, while a cell reference carries its own origin, a fixed point inside the cell. In a flipped FS row that origin lands on the top edge of the row instead of the bottom. In the teaching layout the mirrored row at 8160 and the unmirrored row that starts at 10880 therefore both anchor at 10880. Measure cell outlines, or read the ROW lines, and the pitch is 2.72 micrometers; measure origins alone and you will report double. Do not regenerate the DEF to "fix" that, and do not confuse it with hollow fill. Hollow fill means the cell GDS was never merged. Double origin pitch means a mirrored row, not a broken import. Fix the first by merging. Recognize the second.

The placed rows after the merge, inside the 95 micrometer die: the drawn content spans about 85 by 90 micrometers, and the rows are filled rather than empty boxes.

Zoom into the rows. You are looking for cell interiors plus the signal and power routing from the DEF, and for a row spacing you can compare with 2.72 micrometers in the DEF text.

After import, measure three things and write them down. The GDS carries no die outline: DIEAREA is a DEF statement, so the 95 by 95 micrometers exist in the placement file and not as geometry. What you can measure in the window is the placed content, and here it spans about 85.13 by 90.00 micrometers inside that die. The rows should show interiors, not the hollow labels from the left panel above. The origin spacing you measure on screen is twice the site height; the cell outlines and the DEF coordinates are the ones you keep.

Rules are a deck, not a mood

A design-rule check asks whether polygons obey the process: width, spacing, enclosure, and many more. It does not ask whether the counter saturates or whether the I2C slave acknowledges. A chip can be clean on geometry and still fail the hardware contract.

Each layer has its own limits, and pairs of layers add enclosure. The result is a deck of named checks, hundreds in a real sky130 deck, which is why the teaching run is a macro rather than one click per rule.

Three rule types, as shapes: a strap at least W wide, two shapes at least S apart, and a via inside metal with margin E. A foundry deck is many named checks of these kinds.

In LayoutEditor a rule is a name plus an operation such as minimum size, minimum distance, or enclosure, with the numbers in database units. A full check is a macro that runs many named rules and collects markers. Bind the technology and the layers before you run anything. A wrong layer map produces a flood that looks like a process failure and is really a mapping bug.

Markers on the teaching die. Read the rule name first, width or space or enclosure, after you have confirmed the layer map. Prefer regenerating the DEF over hand-editing the inside of a standard cell.

Triage in that order: layer map, then the named rule, then a fix upstream in placement or routing. This die has no padframe and no foundry signoff claim. A clean teaching run is a learning goal, not a tapeout certificate.

Layout versus schematic compares connectivity extracted from the polygons with the gate-level netlist. It catches an open net and a missing pin. It does not catch swapped A and B logic that keeps the same pin names. That still fails simulation. LayoutEditor can run the comparison. This part only shows the idea.

Two descriptions of the same pins: connectivity taken from the layout, and the gate-level netlist. Agreement here is not a function test and not a geometry test.

You now have a stream whose scale you can measure, whose rows are filled only because the cell library was merged, and whose markers mean a named geometric rule. A padframe and a submission package would be the next engineering steps. They sit outside this series.