Chip tutorial 3: Yosys synthesis for sky130

You want the encoder RTL turned into cells a placer can actually place.

The ports stay. The insides become cells from the foundry library. A NAND, an inverter, a flip-flop with a footprint: that is the vocabulary place-and-route understands. The area number the tool sums from the cell library is a mapping check, not the chip area. Die size shows up only after floorplan, fillers, and a power grid. The sources are in this zip, folder quad-encoder-i2c-yosys. Synthesis maps the design. It does not rewrite the counting rules, and a green run is not a drawing of the die.

RTL goes in. A gate-level netlist comes out. Place, route, and GDS are later parts.

What the run writes, and where it stops

A successful run writes synth/encoder_top_gl.v. Open it and you should see instances such as sky130_fd_sc_hd__nand2_1 and sky130_fd_sc_hd__dfxtp_1, with the top module still named encoder_top. Nets that used to be implied by procedural assignments become wires between cell pins. You do not get coordinates, metal, a padframe, or a timing signoff. You also do not get proof that the counter still saturates. That remains make sim.

Yosys reads Verilog, elaborates the hierarchy, and maps logic onto cells described in a Liberty file. For each cell that file records a name and a Boolean function, and usually area and timing. The mapper needs the function so that !(A&B) can be a nand2_1 and a rising-edge flop can be a dfxtp_1.

Teaching excerpt for sky130_fd_sc_hd__nand2_1: a name and a function the mapper can bind. It is not a foundry screenshot, and it is not a placed cell.

Yosys does not emit DEF or GDS, and it does not print PASS tb_quad_counter. If you need the behavior, re-run the simulator. If you need polygons, that is the next part.

Liberty on your machine, then simulate, then map

You need Icarus Verilog (iverilog, vvp), Yosys with ABC, and one sky130 high-density Liberty file, commonly sky130_fd_sc_hd__tt_025C_1v80.lib (typical process, 25 °C, 1.8 V). Point at your own tree:

export PDK_ROOT=/path/to/your/pdk/root
export PDK=sky130A

The Makefile looks for $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, or for LIBERTY if you set that path yourself. Stay on the HD library. Mixing in another family and then expecting the same cell names is how a map fails in a way that looks like a Verilog bug.

Synthesis maps whatever RTL you feed it, including bugs. Inside the unpacked folder, make sim should print PASS tb_quad_counter before you synthesize. If it does not, stop. make sim-i2c may still fail the ACK check. Mapping does not repair a bus protocol. A clean Yosys run is not evidence that address 0x42 speaks correctly.

The script cannot expand shell variables by itself, so make synth checks that the Liberty file exists, substitutes @LIBERTY@ into synth/synth.ys.in, and runs the generated script. The passes, in order: read the RTL under rtl/ with top encoder_top (testbenches stay out); turn processes into a netlist and optimize; map flip-flops with dfflibmap; map combinational logic with abc; tie constants to conb_1; write synth/encoder_top_gl.v; optionally print stat. The stat area is the number you must not confuse with a floorplan.

Example console, in this order: make sim prints a datapath PASS, then make synth ends by writing synth/encoder_top_gl.v. Your timestamps, cell counts, and paths will differ. The sequence and the netlist write are the claim.

What replaced the always block

After mapping, quad_decoder is no longer a page of always code. It is flops plus a handful of gates for the Gray compare, the ×2 step, and the sticky illegal flag.

A sketch, not a full-chip schematic. Before: the decoder module and its clocked description. After: four dfxtp flops and the gates nand2, inv, nor2, mux2, and a21o. The whole encoder_top is the same idea with many more cells and the same ports.

Swapping this sketch for the console would make the paragraph false. The console is the command order. This drawing is the cell types the decoder becomes.

The check in the netlist

Open synth/encoder_top_gl.v and do three things.

Confirm the ports still match the RTL: clk, rst_n, a, b, z, scl, sda_in, sda_oe, count_o[31:0], illegal_o. Place-and-route hangs constraints on these names. Synthesis must not rename them.

The same port list on both sides: RTL on the left, gate-level netlist on the right. Inside, always blocks have become sky130_fd_sc_hd__ instances. Outside, the names the next tool will bind are unchanged.

Then search the netlist for a cell whose type starts with $. A leftover $adff or $mux means Liberty was missing, the wrong top was selected, or a construct did not map. Treat those hits as failures until explained. Instance types should live in the sky130_fd_sc_hd__ family. Exact instance counts can shift with the Yosys version. Do not judge success by matching someone else's stat line digit for digit.

encoder_top_gl.v and the generated script are outputs. Edit synth.ys.in or the Makefile if you need a lasting change. The next make synth overwrites a hand edit to the generated script. Keep delays and $display out of rtl/. Incomplete combinational blocks infer latches. Asynchronous reset branches in this RTL assign constants; leave them that way.

Glance at any area lines only to see that the cell list is non-empty, then put the numbers away. Route, filler, tap, and power distribution dominate the real outline. The next part is where area becomes a geometric claim. Bring a netlist whose ports match this drawing, whose cells are library cells, and whose simulation still passes.