How a MOSFET is drawn

You want a tiny switch on silicon — something that can let current through when a control voltage says so. On a circuit sheet that switch is a symbol with three pins. On a chip drawing it is not a symbol. It is a stack of colored shapes you look down on, the way you would look at a sandwich from above. That top-view stack is how a MOSFET (metal-oxide-semiconductor field-effect transistor) is drawn.

The picture is a teaching n-channel device, not a taped-out cell from a named factory. A pale well field sits under everything. The green island is active — the silicon where the device lives — covered by an n+ implant window. A gold poly finger crosses the island; that crossing is the gate. Orange contact squares sit on the source and drain ends and on a small poly tab for the gate. Teal metal1 straps land on those squares. Labels mark source (S), drain (D), gate (G), drawn length (L), and drawn width (W). Screen colors are costumes. The stack of sheets is the fact.

The island and the gate strip

Start with the island. Active (shops also say diffusion, OD, or RX) is an opening in the thick field oxide where a transistor is allowed to form. It is not metal. You draw a rectangle, often a few micrometers on a side for a teaching device. The island’s extent under the gate will become the transistor’s width.

Cross that island with a poly strip. Where poly overlaps active, the overlap is the channel — the region the gate will control. Poly must stick past both ends of the island (an endcap) so the channel does not leak at the corners. The strip may continue to a small tab where a contact can reach the gate without sitting on the channel.

Two numbers fall out of that geometry. Drawn length L is about the width of the poly finger where it crosses active — the short dimension of the gate over the island. Drawn width W is about how far active runs under that finger — how “fat” the switch is along the gate. A teaching example: a poly finger about 0.5 µm wide crossing about 2 µm of active gives drawn L ≈ 0.5 µm and W ≈ 2 µm. Swap L and W in your head and you invent a different transistor. Finished silicon may shrink both numbers a little; the drawing still owns the intent.

Flavor, tub, and plugs

Active and poly alone do not finish the device. A heavy implant (often drawn as n-select / n+ or p-select / p+) flavors the source and drain. In the process, poly was already patterned when that dose was fired, so the gate body blocked the implant under the channel — self-aligned source and drain. On the screen the implant window still covers the whole island, including the gate strip; silicon under the gate did not get the dose. Trust the process story, not the thought that every drawn overlap is matter in silicon.

The third picture is the same sandwich with those overlaps named. The channel under the gate is where active and poly meet. Source and drain are where active and n+ meet outside the poly shadow. Contacts are the plugs that climb to metal1. Reading the device is reading those intersections, not counting pretty rectangles.

Which flavor, and which tub, decide nMOS versus pMOS.

On the left, an n-channel device sits in a p-type well (or in the p-type substrate). Green active plus n+ implant, gold poly, contacts, metal1 — the sandwich from the lead figure, drawn smaller. On the right, a p-channel cousin needs an n-well tub and a p+ implant. The active / poly / contact / metal1 habit is the same. The well and the implant are the visible difference. Real processes add more sheets (threshold adjusts, halos, dual wells); the teaching point is already here: device type is a layer recipe, not a color preference.

Those small squares are contacts — the first vertical plugs from metal1 down to active or to poly. They are not vias. A via climbs from one metal floor to another; a contact reaches the silicon parts of the transistor. Each contact needs enclosure by the sheets it joins, and a legal space to the gate. Miss the sheet and you drew a decoration; hang the square off the island and the opening may etch into the field. The longer treatment lives in vias and contacts and enclosure.

One more small habit: a well or substrate tap — a stub of the right active plus a contact — ties the tub to a supply so it does not float. Floating tubs are how latch-up stories begin. The tap is not the MOSFET; it is the neighbor that keeps the bathtub honest.

Why the drawing is a sandwich

A factory builds films and implants from the top down, one mask step at a time. The layout file stores plan-view polygons on named layers, one sheet per job. Looking down, you see the sandwich. Looking from the side, you would see height — gate oxide under poly, source and drain pockets, metal above an insulator — which is why looking at a cross-section exists as a separate lesson. The top view lies about thickness; it tells the truth about which sheets overlap.

Hide every sheet but one, then turn them back on in process order, and the stack becomes readable: well, active, implant, poly, contact, metal. Hiding and showing layers is the everyday way to read that recipe. A process design kit names the sheets and maps their numbers; reading a layer map is how those numbers become words again.

A common mix-up

Beginners treat the colored rectangles as a photograph of metal. They are drawings of process sheets. Another mix-up is believing the schematic MOSFET is the layout. The symbol says which pins exist; the sandwich says where matter goes — cousins, not twins (LVS: layout versus schematic). People also swap contact and via, or read L and W from whichever way the screenshot is rotated instead of from poly-over-active. And because the implant outline covers the gate strip on screen, it is easy to think the channel was dosed. It was not: poly blocked it in the furnace.

Things that go wrong

Poly that stops short of the active edge leaves a leaky endcap. A contact too close to the gate, or hanging off active, fails enclosure or spacing even when the picture still “looks connected.” The wrong implant, or a missing n-well around a pMOS, makes layout versus schematic extract the wrong device — or none. A well without a tap can pass a casual glance and still float. Drawing the whole sandwich on metal layers because the straps looked joined skips the contacts and invents a device the process cannot build.

Boards have copper and drills, not this implant sandwich. Tiny moving machines (MEMS) may reuse poly as a beam and add open or etch-stop sheets — a mechanical recipe, not a gate (MEMS is layout plus a recipe). Photonic kits swap the transistor for a waveguide. The MOSFET sandwich stays the electronics case.

In software

Layout editors, including LayoutEditor, let you draw and color the sandwich sheets, zoom until L and W are measurable, and hide layers one at a time. A PDK’s layer map and display file give those sheets honest names and numbers. Device recognition — “active ∩ poly ∩ select is a MOSFET” — lives in an extraction or LVS recipe from the same kit, not in the paint. The editor shows the drawings. The kit teaches the tool which overlaps mean a transistor. Parameterized cells (PCells) rebuild legal active and poly when you set W and L; the sandwich idea does not change.

When you open a finished cell, look for the island, the gate strip that crosses it, the implant that flavors the ends, the contacts under metal, and the well that holds the flavor. If you can point to each sheet, you can read how a MOSFET is drawn.