Well

Well is a treated tub in the silicon that holds one flavor of transistor and isolates it from the other flavor.

Two islands sit inside the tub. A third island sits outside it.

nMOS and pMOS do not share a bathtub. An n-well might hold pMOS devices. A p-well, or the substrate, holds nMOS, depending on the process. The well drawing is a polygon that must enclosure the active islands, often by 0.4 micrometer or more. A well tap, a contact to the tub, keeps the tub from floating. On the drawing the tub is a large outline around a family of transistors, plus a tap cell every so many micrometers. Latch-up rules are well-tap rules.

A well is a process layer with implant cousins. DRC checks well-to-well space. LVS uses wells to decide which devices are which. Stopping a well at the active edge to save area drops the rim that alignment and sideways diffusion need. The PDK number is not decoration.

Deep n-wells, a triple-well, and isolated p-wells are extra tubs for quiet analog or for battery pins. They cost area and mask count. A 2 micrometer-wide well ring around a bandgap, plus a dedicated tap net, is a usual picture. Crossing a well boundary with active invents a parasitic device. Follow the PDK pictures, not a leftover outline from another process.

The sheet, the process layers, and the rules are covered in what a layer is for, process layers vs drawing layers, and design rules and DRC.