Alignment marks and registration

An alignment mark is a shape in a layout whose only purpose is to let the exposure tool, or the person operating it, place a later mask level on the pattern that an earlier level left on the wafer. Registration is that placement step. Overlay error is its result, measured at a point on the wafer: the position of the current level minus the position of the preceding level, in X and in Y. A lithography-control paper from 2000 defines overlay this way and fits the measured values to a small set of error terms. Alignment marks never become part of a device. They are still ordinary polygons: they must be drawn on the right layers, with the right polarity, at agreed coordinates, or the level that needs them cannot be aligned.

The picture at the top is a LayoutEditor window with one alignment site, drawn for this article. Teal is level 1, the pattern already printed on the wafer. Amber is level 2, the chrome on the next photomask. On the left, the level-1 cross sits in a cross-shaped window cut into a level-2 chrome square, with a narrow gap on every side. The two bar scales are verniers: the horizontal one reads the offset in X, the vertical one the offset in Y. In this drawing, level 2 is shifted 0.3 µm to the right. The cross still looks centered in its window; the X vernier shows the shift, as described in the vernier section below. The geometry uses the default values of the alignment-mark and vernier shapes that ship with LayoutEditor.

Why every level after the first needs marks

The first lithography level has nothing on the wafer to align to. A university cleanroom guide (Cornell NanoScale Facility) states that it is aligned to the wafer flat only, and that the first mask should carry the marks for the next level. Every later level is aligned to marks that an earlier level printed. Course notes on stepper alignment from the Rochester Institute of Technology (RIT), dated 2011, count about 30 aligned layers in a modern CMOS process.

Alignment reduces overlay error; it does not remove it. Layout absorbs the remainder with margins. An enclosure rule, such as metal around a via, keeps metal on every side of the cut so that a shifted level still covers it.

The mark pair

Marks come in pairs, one half on each of the two levels being aligned. The UCSB Nanofab mask guide calls them "matching male+female alignment marks". A common pair is a cross on the earlier level and a box, or a window shaped to fit the cross, on the later level. The Duke Shared Materials Instrumentation Facility (SMIF) photomask guide describes typical marks as a 20 µm square outline with a cross of the same size that fits into the box. The operator, looking through the mask, centers the cross in the box. The clearance between the two halves is the visual tolerance of the alignment: a gap that is visibly unequal on two opposite sides indicates an offset.

Polarity decides whether the mark can be seen at all. In a contact or proximity aligner, the operator views the wafer mark through the mask. Cornell's guide requires the mask-side mark to be clear field: chrome forms the mark, and the glass around it is clear. A dark-field mask, mostly chrome with clear openings, hides the wafer mark under chrome. The Duke guide notes that the words "dark field" and "clear field" are read differently by mask shops and asks for "digital data dark" (drawn shapes become chrome) or "digital data clear" (drawn shapes become clear glass) on the order. The amber square in the lead picture is drawn as "digital data dark": the square is chrome, and the cross-shaped window in it is clear glass. The plate itself is described in what a photomask is.

Which level carries which mark

A process with more than two levels needs a mark pair for every pair of levels that are aligned to each other. Cornell's guide lists two strategies: print the marks for all later levels with the first mask, or let each mask print only the mark for the level after it.

Strategy	Level 1 prints	Level 2 prints	Level 3 aligns to
All marks on level 1	cross A (for level 2), cross B (for level 3)	box A	cross B, from level 1
Each level marks the next	cross A (for level 2)	box A, cross C (for level 3)	cross C, from level 2

The choice changes the error budget. With all marks on level 1, the error of level 3 relative to level 1 is the error of one alignment step. With chained marks, level 3 is aligned to level 2, and its error relative to level 1 is the vector sum of two alignment steps. Chained marks are useful when a later process step covers or destroys the level-1 marks.

Placement on the wafer

On the contact aligners described in the Duke guide, the left and right eyepieces view two marks at the same time. Cornell's guide places two marks on the horizontal axis, at Y = 0 in the layout and near opposite wafer edges, with the wafer flat at the top or bottom of the drawing. Two marks correct X, Y, and rotation. Cornell's tools also accept marks up to about 1 cm above or below the center line. A maskless laser writer measures marks with a camera instead of an operator. The UCSB guide for its Heidelberg MLA150 writer asks for at least four marks, far apart and in different quadrants, so that the tool can also correct scaling and shear.

Tool and source	Number of marks	Placement	Mark size
Contact aligners, Cornell CNF	2	Y = 0, near each wafer edge; up to ~1 cm off the axis	template cell, placed twice at X = ±a
Contact aligners, Duke SMIF	2	same horizontal line, within ±25 mm of the X axis, 55–75 mm apart, centered on the Y axis	20 µm box, 20 µm cross
Maskless writer MLA150, UCSB	4 to 8	far apart, different quadrants	cross, 10–50 µm line width, filling the camera field of 640 × 480 µm (low resolution) or 190 × 140 µm (high resolution)

The coordinates in the file are the coordinates the tool uses. The UCSB guides ask for the design to be centered on (0, 0), for every sub-cell to be drawn around its own origin, and for repeated parts to be placed as cell instances. The MLA150 measures every mark position relative to the file origin. On most UCSB systems the wafer flat is at −Y. For alignment to marks on the back of the wafer, the pattern is mirrored about the Y axis, because the wafer is flipped, and Cornell's guide adds that backside marks must fall inside the windows of the wafer chuck. The conventions for origin and axes are described in origin and quadrants.

Reading the residual offset: verniers

A vernier is a pair of bar rows, one row on each level. The two rows have slightly different pitches. If the pitch of level 2 exceeds the pitch of level 1 by a step Δ, bar pair number n, counted from the center bar, is offset by n·Δ when the levels are perfectly registered. A shift s of level 2 makes the pair with n·Δ = s line up; the reading is the number of the aligned pair times Δ. A patent on two-dimensional verniers states the same relation: the pitch difference sets the resolution, and resolution times the number of bars sets the range. RIT's overlay verniers place the bars of one level on a 10 µm pitch and those of the other on an 11 µm pitch, which gives steps of 1 µm; a finer version halves the step.

The second picture shows two copies of the vernier from the lead picture, shortened to five bar pairs on each side for the close-up. Teal bars are level 1 with a 3.0 µm pitch. Amber bars are level 2 with a 3.1 µm pitch, so Δ = 0.1 µm. In the upper vernier the levels are registered: the long center bars line up, and each other pair is offset by its number times Δ. In the lower vernier, level 2 is shifted 0.3 µm to the right. The center bars no longer line up; the third pair to the left of center does, which reads as +0.3 µm. The generator that drew the figure computes the aligned pair from the polygon coordinates.

Verniers are read with an optical microscope, usually right after development, when a misaligned resist layer can still be stripped and exposed again. A 2014 study on electron-beam alignment gives about 50 nm as the typical precision and accuracy of such optical verniers. RIT's notes warn that some microscopes invert the image and ask that every correction be written with its direction, for example "shift in −Y, toward the flat".

Measuring overlay in production

Production lines measure overlay with dedicated targets and an imaging metrology tool. The most common target is box-in-box: an outer box printed with the earlier level and an inner box printed with the current level. A patent on segmented targets gives about 20 µm for the outer box and about 10 µm for the inner box, with four targets at the corners of each exposure field. The tool locates the center of each box from its edges; the difference of the two centers is the overlay error at that site.

One site gives a translation. Many sites give the error terms of the exposure: translation in X and Y, rotation, magnification or scale, and orthogonality, separately for the whole wafer and for each exposure field. The paper from 2000 fits these terms by least squares over the measured sites; each term has an adjustable parameter in the exposure recipe, which is corrected for the next lot. The same terms explain the placement rules above: two marks on one axis give translation and rotation, and the MLA150 guide asks for marks in different quadrants to measure shear and orthogonality.

Steppers, scanners, and foundry processes

A stepper or scanner aligns automatically. The RIT notes for an ASML PAS 5500 describe wafer marks that are diffraction gratings for X and Y, read with a helium-neon laser at 632.8 nm. One scribe-line mark in those notes has 8.0 µm lines on a 16 µm period and a length of 72 µm. Marks of this kind are printed at the first level or in a separate zero level before any device level; a grating etched to a depth of λ/4n, about 110 nm, gives maximum contrast. The reticle carries its own fiducial marks, which align the plate to the tool. The notes also list the problem that later steps create: polishing, oxide growth, and metal deposition change the appearance of a mark, can turn a trench into a mesa, and can bury a mark completely. The alignment strategy, including clear-out exposures over marks, is therefore part of the process design and of the chip layout.

The RIT notes call such marks street marks: they sit in the scribe streets between dies. Submission rules show where a foundry customer's data ends. One 2026 Europractice multi-project schedule asks for a single GDS file enclosed with the foundry's seal ring and an 80 µm scribe; its list of customer items contains no alignment marks. Designers who own the process, as in most MEMS and university cleanroom work, draw the marks themselves, as the facility guides above require. Reticle layout and field size are covered in steppers and why size matters, the full sequence in from idea to mask.

Electron-beam writers

An electron-beam writer finds marks by the electrons they scatter back. The Minnesota Nano Center guide for its EBPG writer recommends heavy metals such as gold or platinum, 30–50 nm thick, for strong contrast against silicon. Etched marks have no material contrast and need a depth of at least one micrometer. The guide prefers rectangles to crosses, because the writer finds rectangles from a less precise starting position. It accepts mark sizes up to 100 µm, recommends a width of at least 10 µm, and asks for about 50 µm of empty space around each mark, because nearby structures disturb the search.

A drawn offset is a built-in error

The operator centers the cross in its window. If the two halves of a pair were drawn off-center relative to each other, centering them on the aligner shifts every device on level 2 by the drawn offset. The alignment step does not reveal this; a correctly drawn vernier or overlay target shows it only after exposure. Drawing both halves in one cell with one origin prevents this; a mark pair copied from a template, or assembled from two cells, should be checked. The following LayoutEditor rule deck checks the drawn gap between the halves:

units 1e-6

layer level1 = input(1, 0)    # cross, prints with mask level 1
layer level2 = input(2, 0)    # square with cross-shaped window, mask level 2

# a drawn offset between the two halves shows up as a gap below 1 um on one side
check "AM.gap" "AM.gap : level-2 window clears level-1 cross by >= 1.000 um" : sep(level1, level2) < 1 um

# an offset larger than the gap makes the halves overlap
layer clash = level1 & level2
output clash "AM.overlap" "AM.overlap : level-1 cross overlaps level-2 chrome"

sep measures the outside distance between the two layers; the & line reports any area where the cross overlaps the chrome. The deck was run with layout --drc on four test pairs: a correct pair (nominal), level 2 shifted by half the gap in X (shift_0.5), a window drawn with half the gap (gap_0.5), and level 2 shifted by one and a half times the gap (shift_1.5):

nominal    AM.gap 0   AM.overlap 0
shift_0.5  AM.gap 3   AM.overlap 0
gap_0.5    AM.gap 12  AM.overlap 0
shift_1.5  AM.gap 0   AM.overlap 3

The third picture is the shift_0.5 pair. The window, and the chrome around it, sits half a micrometer to the right of the cross. On the left, the end of the horizontal arm and the left edges of the upper and lower vertical arm face the chrome at half the gap; the three red strips are the reported markers. On the right, the gap has grown to one and a half micrometers, which the rule does not flag. The 12 markers of the gap_0.5 case are the 12 edges of the cross.

In LayoutEditor

LayoutEditor ships a Parametric Shape Library with an Alignment Mark shape and a vernier shape named Nonius. According to the manual, the shapes are placed from the Components window of the SchematicEditor. The defaults, read from the shape macros of the installed version:

Shape	Parameter	Default	Meaning
Alignment Mark	size	50 µm	span of the cross on layer_1
Alignment Mark	thickness	10 µm	arm width of the cross
Alignment Mark	space	1 µm	gap: the window on layer_2 is the cross grown by this value
Alignment Mark	boxsize	65 µm	chrome square on layer_2 around the window
Nonius	size	2 µm	bar width along the measured axis
Nonius	space	1 µm	space between bars of layer_1
Nonius	nonius	0.1 µm	pitch difference Δ of layer_2
Nonius	steps	10	bar pairs on each side of the center bar; range ±1.0 µm

Both macros name the generated cell after its parameters and reuse an existing cell with the same name, as described in PCells: cells with knobs.

The same mark pair can be written with LayoutScript, the Python interface of LayoutEditor. This script builds the pair as one cell and places it twice on Y = 0, 60 mm apart, within the Duke spacing:

from LayoutScript import *

def cross(half, arm, grow=0):
    """12 corners of a cross centered on (0, 0); all values in nm."""
    a, h = arm + grow, half + grow
    return [(a, a), (h, a), (h, -a), (a, -a), (a, -h), (-a, -h),
            (-a, -a), (-h, -a), (-h, a), (-a, a), (-a, h), (a, h)]

def polygon(cell, pts, layer):
    pa = pointArray()
    for x, y in pts:
        pa.attach(x, y)
    cell.addPolygon(pa, layer)

d = project.newLayout().drawing           # 1 dbu = 1 nm
mark = d.addCell().thisCell
mark.cellName = "AM_L1_L2"
polygon(mark, cross(25000, 5000), 1)       # level 1: cross 50 um, arms 10 um
w = cross(25000, 5000, grow=1000)          # level 2: window 1 um larger
b = 32500                                  # level 2: 65 um square around it
polygon(mark, w[:2] + [(b, w[1][1]), (b, b), (-b, b), (-b, -b), (b, -b),
                       (b, w[1][1])] + w[1:], 2)
top = d.addCell().thisCell
top.cellName = "WAFER"
for x in (-30000000, 30000000):            # X = -30 mm and +30 mm, Y = 0
    top.addCellref(mark, point(x, 0))
d.saveFile("align_marks.gds")
print("ok", mark.cellName, "placed at x = -30 mm and +30 mm, y = 0")

ok AM_L1_L2 placed at x = -30 mm and +30 mm, y = 0

The level-2 polygon is the square with the window cut in along one line, the way GDSII stores a polygon with a hole (see holes in polygons). The rule deck above reports no markers on this file:

layout --drc align_gap.ledrc align_marks.gds --outdir=drc_out

Things that go wrong

Failure	Effect	Check in the layout
Mark drawn on a layer that is not ordered as a mask	no mark on the wafer; the next level cannot be aligned	every mark layer appears on the mask order
Mask-side mark in a dark-field area	wafer mark hidden under chrome (Cornell)	mask mark is chrome in clear glass
Polarity written as "dark field"/"clear field" only	risk of a plate with inverted polarity (Duke)	order says "digital data dark" or "digital data clear"
Design not centered, or origin not at wafer center	mark coordinates do not match the tool positions (UCSB, MLA150)	top cell centered on (0, 0); marks at the tool's coordinates
Backside marks not mirrored, or outside the chuck windows	backside alignment impossible (UCSB, Cornell)	mirrored copy; positions inside the windows
Mark buried or flattened by later steps	alignment signal lost (RIT)	clear-out windows over marks, or chained marks
Mark smaller than the camera field	automatic alignment fails (MLA150)	cross fills the field
Other structures next to an e-beam mark	mark search fails (Minnesota)	about 50 µm of empty space
Drawn offset between the two halves	the same overlay error on every wafer, visible only on verniers or overlay targets after exposure	both halves in one cell; sep check above

Before a mask order goes out, list for every level the mark it prints, the mark it aligns to, the layer number of each, the polarity of each plate in "digital data" terms, and the coordinates of every mark relative to the wafer center. If any level has no partner mark on an earlier level, that level cannot be aligned by the tool it is planned for.