Nets, pins, and labels on a layout

You need the clock on a chip to be one electrical node wherever the circuit expects it — not a scatter of shapes that only look related. On a schematic that node has a name. On a layout the stream file stores polygons, paths, and text. It does not store a netlist by itself. Connectivity is built from geometry that touches, then named by labels and pins so tools and people can say which node they mean.

The picture is a teaching cell, not a taped-out standard cell from a named factory. An orange pin square sits on the left edge where a connection is allowed to enter. Teal metal1 landings join through straps into one continuous conductor. An orange via climbs into navy metal2 on the right, so the same node can change floors. Black text objects spell clk on a label layer over that joined metal. Those strings are not captions burned into this article; they are layout text. Screen colors are costumes. The claim is simpler: joined conductors plus the same name make one net.

Why names matter on shapes

Shapes on the same layer become one piece of metal when they touch. Shapes on different layers join only through a contact or a via. That physical habit is the cousin of a schematic wire (LVS: layout versus schematic). The schematic already chose a name — clk, vdd, out. The layout must build the tree of metal and cuts that extract back to that name.

A stream format such as GDSII can carry a text record: a string, a position, a size, a layer. It cannot carry “these fifty shapes are node clk” as a first-class netlist. Extraction walks overlaps and vias, then attaches names from text objects whose layers the process recipe connects to the conductors. Without that attachment, the metal is still metal. It is not yet a named net to a checker.

Labels name the metal you already joined

A label in this sense is a text object on a layer the connectivity recipe treats as a naming layer — often a dedicated datatype beside the metal drawing layer. When extraction connects that label layer to metal1, the string becomes the net name for every conductor in the same connected piece. Put clk on three joined landings and you still have one net. Put clk on a fourth island with daylight in between and you have two nets fighting over one name.

The second picture separates jobs that look alike on a colorful screen. On the left, an orange pin square and teal metal carry the label A on a naming layer — geometry a router or extractor can treat as access to net A. On the right, the letters NOTE / leave empty sit on a remark layer with no conductor under them. A person can read them. A connectivity recipe that never attaches that layer will not invent a net named NOTE. Text on a layout already warns that remarks left on a manufacturing layer can become chrome; here the twin warning is the opposite miss: pretty letters that never join the naming recipe leave the net unnamed for tools.

Pins are doors, not stickers

A pin is where a named net is allowed to enter or leave a cell. Routers, abstract views, and layout-versus-schematic checks need a place, not only a hope. The place is often a rectangle on a legal metal, plus a name that matches the schematic or the published abstract. Digital library formats publish those pin boxes so a place-and-route tool can land wires without opening the transistors inside. The GDS you ship for compare still needs names and access consistent with that contract.

A sealed drawing with no pins is a black box to a router. Letters floating near the edge without access geometry are stickers. Stickers help people; pins help the machine decide where a connection may land. Miss the mark and a wire sits on blockage, or an extractor never sees a port where the schematic listed one.

When names and joins disagree

The third picture is the naming version of short and open. On top, one continuous metal1 strap carries two different strings, vdd and out. The shapes are one conductor. The names disagree. Extraction that attaches both labels to that metal sees one net with a conflicted identity — the naming form of a short against a schematic that kept those nodes apart. On the bottom, two islands both say clk, with a visible gap (drawn red here only as a teaching mark). The names agree. The metal does not. That is not one net; it is a name collision across an open.

Layout versus schematic compares the list pulled from geometry to the list taken from the sheet. A missing via under a confident bar is an open of joins. Two different labels on one strap, or the same label on two islands, are opens and shorts of names. Zoom will not sort which failure you have. The report will.

A common mix-up

Beginners treat any readable text as a net name. Only text on layers the connectivity recipe attaches actually names a net. Another mix-up is believing the schematic wire title is already metal — cousins again, not twins. People also confuse a pin with a label: a pin needs access geometry; a label names a conductor; a remark helps a human. And because GDS hierarchy can stamp a leaf many times, port labels that only live deep inside a child cell can be the wrong story for a top-level compare that expects instance-specific names at the top of the view you are checking.

Things that go wrong

Two different labels on one strap make a short of names. The same label on two islands with daylight between them makes an open while the screen still says clk twice. A pin box missing while letters remain fools a review and fails a router. A label on the wrong layer number is as missing as no label, if the recipe never attaches that layer. Construction notes on metal print as chrome (text on a layout); construction notes on a true remark layer never name vdd for LVS. Updating the schematic net name and forgetting the layout text leaves a clean picture and a dirty compare.

Boards have copper nets and pad names in footprints — the same idea with different file habits (PCB copper is also a layer, footprints are almost cells). Tiny moving machines and photonics still need named ports where light or fluid leaves a cell; the metal-and-via story here is the electronics case.

In software

Layout editors, including LayoutEditor, let you place text objects and pin shapes on named layers, zoom until a gap is visible, and hide remark layers so only naming text remains. A process design kit’s connectivity or LVS recipe decides which text layers attach to which conductors. The editor paints the letters. The recipe decides whether those letters become net names. Highlight a net after extraction and a tree of metal and vias lights up under one string — that is the payoff for keeping joins and names honest.

When you open a cell, look for the pin access on the edge, the labels on the conductors you meant to join, and the daylight you meant to keep. If you can point to the door, the name, and the metal that carries it, you can read nets, pins, and labels on a layout.