Antenna rules: charge during etch

Antenna rules limit how much conductor area may be connected to a transistor gate while the chip is still being manufactured. During fabrication, a wire can be connected only to the gate it drives, with no other path for electric charge. The plasma that patterns the wire charges it. If the wire is long and the gate is small, the charge can break down the gate before the chip is ever powered. In the finished chip the same wire is an ordinary connection from one driving block to one gate on the other side of the die.

The picture is a teaching layout, not a cell from a real product. The beige field is the silicon substrate. Bottom left is the receiving transistor: a green active island crossed by a gold poly strip. The gate is the overlap of the two, 0.5 µm by 2 µm, which is 1 µm². The poly runs to a contact and a dark metal1 pad. From that pad a long metal1 wire folds back and forth across the frame. Top left is the driving transistor. The thin outlined path between the end of the wire and the driver is metal2. It is drawn as an outline because the picture shows the moment when metal1 is being patterned and metal2 does not exist yet. At that moment the gate is connected to roughly 124 µm of wire and to nothing that can discharge it.

Why it matters

A transistor gate sits on an insulating film, the gate oxide, which is only a few nanometers thick in modern processes. The thin oxide is what lets a small voltage control a large current, and it is the most fragile structure on the chip. If enough charge accumulates on the gate side, current is forced through the oxide. A large dose breaks it down and the transistor fails. A smaller dose leaves damage: trapped charge, a shifted threshold voltage, or reduced oxide lifetime. Such a device can pass the factory test and fail later in the field. Researchers measure the effect with test structures that connect very large antenna conductors to very small gates.

The problem cannot be seen in the layout. The wire has legal width, legal spacing, and the correct connections, and the finished circuit is correct. The failure depends on the order in which the factory builds the layers, and a top view does not show that order.

How it works

Layer order

A chip is built from the silicon upward: transistors, then contacts, then metal1, then the first via layer, then metal2, and so on. Each metal layer starts as a film over the whole wafer. A mask pattern protects the drawn shapes, and a plasma (an ionized gas) etches away the rest. The cross-section article shows the stack from the side; for antenna rules the relevant property is the sequence. While metal1 is etched, no layer above it exists. A metal1 shape is connected only to what it reaches through lower layers.

Charge collection and discharge

The plasma deposits charge on every exposed conductor, approximately in proportion to its exposed area: the top of a freshly etched wire and, in many processes, its sidewalls. Industry documents call such a conductor a process antenna; the term has nothing to do with radio.

If the wire is connected to silicon diffusion, such as the source or drain of a transistor, the charge flows into the substrate without damage. If the wire is connected only to a gate, the charge can only discharge through the gate oxide. The lead picture shows this case: the driver's diffusion is connected later through metal2, but during the metal1 etch the gate has no other discharge path.

The antenna ratio

Foundries express the limit as a number. The antenna ratio is the exposed conductor area on a net divided by the gate area connected to it, and the process sets a maximum. A larger gate tolerates more charge, so a wide transistor allows a longer wire than a minimum-size one.

The open SkyWater SKY130 process kit publishes its table:

Layer	Measured area	Maximum ratio
metal1	sidewall: perimeter × metal thickness (0.35 µm)	400
poly	—	50
contacts and vias	bottom area	as low as 3 to 6

For a 1 µm² gate, the metal1 limit is 400 µm² of sidewall area. That corresponds to about 1,140 µm of perimeter, which a long thin wire reaches at roughly 570 µm of length. The wire in the lead picture is shortened to fit the frame: 124 µm of 0.6 µm wide metal1 gives a sidewall ratio near 87, which is legal in that process. A wire five times as long fails.

Two refinements matter in practice:

• Partial ratio: the check runs layer by layer. For each layer it counts only what is connected through lower layers at the time that layer is etched.
• Cumulative ratio: many processes also sum the contributions of several layers along the net.

The numbers and measurement rules belong to each factory's process design kit. A table from another process does not apply.

An antenna check differs from width and spacing checks. A width rule evaluates one shape. An antenna rule needs to know which shapes form one net, where the gates are, their area, and the order of the layers. It is a connectivity check, related to layout versus schematic, although it usually runs as part of DRC.

Fixing it in the drawing

Both standard repairs change the geometry, not the circuit.

The first repair is a jumper: the wire is cut near the gate, and the gap is bridged on a higher layer. In the second picture the gate keeps only a short metal1 stub. A via connects it to a blue metal2 bridge, and a second via connects the bridge back to the long metal1 run. During the metal1 etch, the gate is connected only to the stub, and the long run is connected to no gate. When metal2 is etched, the bridge completes the net, and the net already reaches the driver's diffusion, which provides the discharge path. A jumper is most effective close to the gate it protects. It costs some area on the upper layer and two additional vias; the vias and contacts article covers the rules for each via.

The second repair is an antenna diode: a small n-type diffusion island in the p-type substrate, connected to the gate's net on the lowest possible layer. In the third picture it is placed directly left of the gate pad. In normal operation the diode is reverse-biased and has almost no effect on the circuit. During manufacturing, its leakage provides a discharge path to the substrate. Rule tables usually grant a diode additional allowance; SKY130, for example, adds a fixed amount plus an amount that increases with diode area. A diode adds a small amount of area, capacitance, and leakage to the net. Digital flows insert ready-made diode cells automatically; analog designers often draw them by hand.

Other remedies:

• route the long wire on the top metal, which is etched last;
• move the driver closer to the gate;
• split a long net with a buffer.

All remedies have the same aim: no large exposed conductor on a small gate without a discharge path.

A common mix-up

The name is misleading in two ways. First, antenna rules do not concern radio pickup or signal noise in the operating chip; they concern charge during manufacturing. Second, a layout that violates an antenna rule can be electrically correct, because the rule describes a state before the circuit is complete. A further misconception is that only long metal counts. Poly lines, contacts, and vias have their own limits, and the lowest SKY130 limits apply to the cut layers.

Things that go wrong

• A jumper placed far from the gate leaves a long section connected, and the violation remains.
• A diode connected through metal2 does not fix a metal1 violation, because it is not yet connected when metal1 is etched.
• A diode drawn under poly or merged into a substrate tap may not be recognized as a diode by the kit's rules.
• A gate wired directly to an input pad: the pad is a large metal area and there is no driving diffusion on the chip. This is one reason input pads have protection diodes.
• Antenna diodes do not appear in the schematic. SkyWater's documentation states that they must not be reported there, so the LVS setup has to ignore them.
• Without the cumulative ratio, each layer can pass on its own while the net as a whole fails.

In software

LayoutEditor's design-rule language includes an antenna check. First declare which layers connect (connect gate, poly, connect poly, contact, connect contact, m1). Then write a check such as antenna(gate, m1) > 100. Without the connect lines the check has no nets to evaluate.

The check forms one ratio per connected net. Numerator and denominator use the same measurement. With the default how=area, the ratio is metal area divided by gate area. With how=perimeter, it is metal perimeter divided by gate perimeter. A diode= layer with factor= greater than zero enlarges only the denominator: metal / (gate + factor × diode). accumulate=yes sums every non-gate shape on the net. The marker is the gate shapes of that net; output=metal marks the metal instead. The check does not use metal thickness, sidewall area, a diode subtracted from the metal, or a process bonus.

That formula is not the SkyWater SKY130 metal1 antenna rule. SKY130 .met1.1 measures sidewall area as perimeter × metal thickness 0.35 µm and limits the ratio to 400. On a measured probe, a 560 µm × 0.14 µm metal1 wire on a 1 µm² gate scores 78.4 under LayoutEditor's area ratio and 392.1 under that sidewall formula. Sign-off against a process table remains the foundry deck.

Automated digital flows carry related limits in their abstract cell files: LEF has keywords for gate area, diffusion area, and allowed ratios, and the router can insert diode cells where a net fails. In every tool the limits come from the factory's kit. The layout editor is used to draw the stub, the jumper, or the diode; the checker computes the ratios.